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DA14530 Datasheet(PDF) 73 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 73 Page - Renesas Technology Corp |
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73 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 73 of 332 © 2021 Renesas Electronics 12 DMA Controller 12.1 Introduction The 4-channel direct memory access (DMA) controller transfers data of eight bits, 16 bits, or 32 bits between the on-chip supported peripherals (SPI, UART, UART2, I2C, and ADC) and the on-chip RAM and supports regular memory-to-memory transfers. The DMA also supports a programmable interrupt generation to generate an interrupt after a certain number of transfers in order to off load the Cortex interrupt rate. The on-chip peripheral requests are multiplexed on the two available channel pairs to increase the DMA utilization. A block diagram of the controller is depicted on Figure 18. Features ● Four channels with an optional peripheral trigger ● Full 32-bit source and destination pointers ● Flexible interrupt generation ● Programmable length ● Flexible peripheral request per channel ● Option to initialize memory (DMA_INIT) ● Programmable edge-sensitive request support (recommended when writing to UART/UART2 and I2C) DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 SPI RX/TX req I2C RX/TX req other req . . . SPI RX/TX req I2C RX/TX req other req . . . SPI RX/TX ack I2C RX/TX ack other ack . . . SPI RX/TX ack I2C RX/TX ack other ack . . . Control DMA01_REQ_MUX DMA03_REQ_MUX APB16 AHB Lite Block IRQ lines IRQ lines DMA IRQ lines Figure 22: DMA Controller Block Diagram 12.2 Architecture 12.2.1 DMA Peripherals By default, the DMA assumes memory-to-memory transactions. Each DMA channel can also be connected with the hand-shaking signals or other request signals of the corresponding peripherals (Table 38). |
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