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DA14530 Datasheet(PDF) 71 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 71 Page - Renesas Technology Corp |
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71 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 71 of 332 © 2021 Renesas Electronics The DMA engine internally supports the following burst types: ● Eight words incremental burst (INCR8) ● Four words incremental burst (INCR4) ● Unspecified incremental burst (INCR) with a length different from 1, 4, or 8 ● Single word access (SINGLE) The slave block combines two AHB slave interfaces: one is for the registers and can be read from/written to, and the other is for the contents of the OTP memory and is read-only. The OTP controller configures the OTP cell to be in one of the following modes: ● Deep Stand-by Mode (DSTBY). In this mode the required power supplies are applied to the OTP cell, while the internal LDO of the OTP cell is inactive. ● Stand-by Mode (STBY). In this mode, the OTP cell is disabled by deactivating the chip select signal. The OTP cell is powered and the internal LDO is enabled. The power consumption of the OTP cell in this mode is not the minimum possible but is less than in an active mode (RD, PROG, PVFY, RINI, AREAD). This is the state from which any active mode of operation can be transitioned into with the least delay. ● Read Mode (RD). When this mode is used, the contents of the OTP cell can be read at the respective AHB address space. This mode can also be used to execute software in place (XIP). A read request is translated by the OTP controller into the corresponding control sequence for the OTP cell in order to retrieve the requested data. ● Programming Mode (PROG). The PROG mode provides the functionality to program a 32-bit word into an OTP position. The OTP cell expands the 32-bit word by calculating and automatically appending a 6-bit checksum (ECC). Please note that there is no way to access these extra six bits of the ECC information. Programming is performed only for bits equal to 0. Bits equal to 1 are bypassed to save programming time. Because the ECC value is unknown to the controller, there are always six extra programming pulses applied to the ECC bits. Programming is done by issuing a programming request stored in the Programming Buffer (PBUF). PBUF consists of two configuration registers storing the 32-bit data value and the 13-bit address in the OTP cell where the value should be programmed. A new request can only be stored in PBUF when the previous is served. A status bit indicates whether this has already been done, therefore programming should be monitored by SW before a new programming request is issued. ● Programming Verification Mode (PVFY). The PVFY mode forces the OTP cell to enter a special margin read mode. This mode is used to verify the content of the OTP positions that have been programmed using the PROG mode and to verify that the programmed data is retrieved correctly under all corner cases. When this mode is used, the contents of the OTP cell can be read at the respective AHB address space. The CPU must read all OTP positions that have been programmed by accessing the corresponding addresses and verify that all the retrieved words are equal to the expected values. ● Read Initial State Mode (RINI). The RINI mode implements a production test of the initial margin read, which should be performed in the OTP cell, before the first programming is applied. This test verifies that the OTP cell is empty (all the bits are equal to 1). The OTP controller will send the required control sequence to the OTP cell to enables the test mode. Then the CPU should read all the content of the OTP cell at the respective AHB address space and verify that all the retrieved words are equal to 0xFFFFFFFF. The RINI mode should be used after the PROG mode in order to verify the content of the OTP positions that have been programmed and specify the bits that remain un-programmed. This verification is required to ensure that the programming process has not affected the un-programmed bits. This specific read mode is a margin read, which means that it is not an equivalent to the normal read and should only be used for the purpose of verification. ● Automatic Read Mode (AREAD). This mode is used to mirror large parts of the OTP cell into RAM through the AHB master interface and the integrated DMA controller. Transitioning from one mode to another automatically steps through the STBY mode. |
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