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DA14530 Datasheet(PDF) 64 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 64 Page - Renesas Technology Corp |
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64 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 64 of 332 © 2021 Renesas Electronics 10 Clock Generation 10.1 Clock Tree The generation of the system's clocks is described in detail in Figure 17. LDO_CORE CP (512KHz) XTAL32M OSC RC32M OSC RC OSC 32K/512K hclk ble_hclk spi_clk Divide by HCLK_DIV uart_clk uart2_clk tmr0_clk rfcu_clk Divide by BLE_DIV ble_crypt_clk ble_master1_clk ble_master2_clk arb_clk ble_lp_clk RCX OSC XTAL32K OSC CLK_CTRL_REG[LP_CLK_SEL] CLK_CTRL_REG[SYS_CLK_SEL]==0x0 Divide by PCLK_DIV apb_clk wakeupct_clk otp_clk i2c_clk Divide by TMR_DIV Divide by 2 CLK_PER_REG[I2C_ENABLE] CLK_PER_REG[UART1_ENABLE] CLK_PER_REG[UART2_ENABLE] CLK_PER_REG[TMR_ENABLE] CLK_PER_REG[WAKEUPCT_ENABLE] CLK_AMBA_REG[OTP_ENABLE] CLK_RADIO_REG[BLE_ENABLE] CLK_RADIO_REG[RFCU_ENABLE] CLK_PER_REG[QUAD_ENABLE] quad_clk System Clocks Peripheral Clocks BLE & Radio Clocks CLK_PER_REG[SPI_ENABLE] 1 0 TIMER0_CTRL_REG[TIM0_CLK_SEL] gp_adc_clk GP_ADC_CTRL_REG[GP_ADC_EN] Divide by 10 tmr0_on_clk 0 1 TIMER0_CTRL_REG[TIM0_CLK_SEL] gen_por_timer PLL DIV 2 rtc_clk lp_clk sys_clk Divide by RTC_DIV DIV=>10,24ms wdog_clk 1 0 TIMER1_CTRL_REG[TIM1_CLK_SEL] tmr1_clk 0 1 0 1 wokenup & !(CLK_CTRL_REG[SYS_CLK_SEL]&0x2) DIV 2 P0[3] spi_fast_clk 0 1 XTAL32M RC32M CLK_CTRL_REG[SYS_CLK_SEL]=0x0 0 1 2 3 Analog startup FSM wakeup_clk tmr2_clk 1 0 TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_CLK_SEL] Figure 17: Clock Tree Diagram Figure 17 depicts the possible clock sources as well as all different divisions and multiplexing paths towards the generation of each block's clock. Furthermore, the required registers that have to be programmed are also shown in Figure 17. |
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