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DA14530 Datasheet(PDF) 62 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 62 Page - Renesas Technology Corp |
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62 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 62 of 332 © 2021 Renesas Electronics 9 Memory Controller 9.1 Introduction The Memory Controller of DA14531 is responsible for the interface between the memory cells and the masters of the system that request access. It comprises two arbiters which use a fixed priority level scheme to allow parallelization between the three main masters of the RAM. The memory controller also provides the actual physical sequence of the RAM cells in a continuous memory space to enable the activation of the required amount of SysRAM only in order to save power. The block diagram is presented in Figure 16. Features ● Three different capacities for the RAM cells with retention capability (12 kB, 16 kB, and 20 kB) ● Arbitration among the AHB masters (CPU or DMAs), OTP, and the BLE core ● Transparently interfaces the AHB busses to memory signaling ● Fixed arbitration algorithm with time sharing Memory Controller System AHB bus BLE memory bus Arbiter MUX-DEMUX Memory bus Arbiter Figure 16: Memory Controller Block Diagram 9.2 Architecture The Memory Controller contains two Arbiters which connect to the following busses via a Mux- Demux: ● BLE Mem I/F: this is a memory interface directly from the Bluetooth 5.1 Core to the RAM used as an exchange memory (TX/RX descriptors and others). This interface always operates at 16 MHz ● System Mem I/F: This is a memory interface directly from the OTP memory to the RAM used for copying data after power-up/wake-up 9.2.1 Arbitration The arbitration is a mixture of the highest priority and a fair use policy. If more than one master request access to cells which reside under the same arbiter, time division is employed. This is to |
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