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DA14530 Datasheet(PDF) 58 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 58 Page - Renesas Technology Corp |
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58 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 58 of 332 © 2021 Renesas Electronics 7 AMBA Bus 7.1 Introduction The DA14530 is based on the AMBA 2.0 AHB and APB components. The AHB is an AMBA Lite version which requires a single master on the system, but there is arbitration between the Arm Cortex-M0+ CPU and the Direct Memory Access (DMA) engine. There are two APB bridges, one for APB16 and the other for APB32, implementing three different decoded slaves which are grouped according to the power domain structure of the chip. The AMBA bus organization is presented in Figure 15. PD_SYS Memory Controller Arm Cortex- M0+ Access from BLE Controller RFCU BLE Controller Clockless Wakeup Quad Decoder Clocked Wakeup GPIO Timer0,2 GPRG WatchDog UART UART2 I2C SPI ADC AHB master AHB master Sys RAMs Access to Memory Controller RTC Timer1 BLE Timer PMU/CRG Keyboard OTP Controller & Memory APB16 Bridge APB32 Bridge ROM DMA Figure 15: AMBA Bus Architecture and Power Domains 7.2 Architecture Since the DA14530 consists of several different power domains that are digitally controlled and can be shut down completely, various slave resources, especially on the APB bus, are grouped together to reduce signal isolation requirements. On the AHB Lite bus, the CPU or the DMA can be the master, while OTP, BLE Core, Memory and ROM controllers are slaves. The Always On power domain (PD_AON) contains only the clock-less wake-up controller and the start-up hardware FSM responsible for the activation of the power devices within the system. The sleep power domain (PD_SLP) contains the clock tree, the BLE Timer, the Clocked Wake-up Controller, and the Quadrature Decoder. These blocks are supposed to trigger or to capture wake-up events while the system is in any of the clocked sleep modes. The timers power domain (PD_TIM) contains special purpose timers that might or might not be crucial for an application: a full featured Real Time Clock (RTC) engine and Timer1. The registers of these blocks are 32-bit wide, hence they are connected to the APB32 bus. The APB16 bus connects to the radio power domain (PD_RAD), which consists of the Radio control unit and the BLE controller, and to the peripheral blocks which are all part of the same power domain as the CPU (PD_SYS). |
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