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DA14530 Datasheet(PDF) 57 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 57 Page - Renesas Technology Corp |
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57 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 57 of 332 © 2021 Renesas Electronics To access the Cortex-M0+ NVIC registers, the Cortex Microcontroller Software Interface Standard (CMSIS) functions can be used. The input parameter IRQn of the CMSIS NVIC access functions is the IRQ number. This can be the IRQ number or (more conveniently) the corresponding IRQ name listed in Table 34. For example, the corresponding interrupt handler name in the vector table for IRQ#15 is SPI_Handler. For more information on the Arm Cortex-M0+ interrupts and the corresponding CMSIS functions, see section 4.2 Nested Vectored Interrupt Controller in the Cortex-M0+ Devices Generic User Guide. The Watchdog interrupt is connected to the NMI input of the processor. 6.2.2 System Timer (systick) The Cortex-M0+ System Timer (SysTick) can be configured for using two different clocks. The SysTick Control & Status (STCSR) register specifies which clock should be used by the counter. ● STCSR[CLKSOURCE] = 0: use the (fixed) external reference clock STCLKEN of 1 MHz ● STCSR[CLKSOURCE] = 1: use the (HCLK_DIV dependent) processor clock SCLK (for example, 2, 4, 8, or 16 MHz) The default SysTick Timer configuration uses the (fixed) external reference clock STCLKEN (STCSR[CLKSOURCE] = 0). When necessary, higher clock frequencies can be used with STCSR[CLKSOURCE] = 1, but the software should take the HCLK_DIV dependent core clock SCLK into account about the timing. 6.2.3 Wake-Up Interrupt Controller The Wake-up Interrupt Controller (WIC) is a peripheral that can detect an interrupt and wake the processor from Extended Sleep mode. The WIC is enabled only when the SLEEPDEEP bit in the system control register is set to 1 (see System Control Register in the Cortex-M0+ Technical Reference Manual). The WIC is not programmable and does not have any registers or user interface. It operates entirely from hardware signals. When the WIC is enabled and the processor enters Extended Sleep mode, the power management unit in the system can power down most of the Cortex-M0+ processor. This has the side effect of stopping the SysTick timer. When the WIC receives an interrupt, it takes a number of clock cycles to wake up the processor and restore its state before it can process the interrupt. This means the interrupt latency is increased in Extended Sleep mode. 6.3 Programming For more information on the Arm Cortex-M0+, see the documents listed in Table 35. Table 35: Arm Documents List Document Title Arm Document Number 1 Cortex-M0+ Devices Generic User Guide Arm DUI 0662B (available on the website) 2 Cortex-M0+ Technical Reference Manual, r0p1 Arm DDI 0484C (available on the website) 3 Armv6-M Architecture Reference Manual Arm DDI 0419C (can be downloaded by registered customers) |
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