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DA14530 Datasheet(PDF) 56 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 56 Page - Renesas Technology Corp |
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56 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 56 of 332 © 2021 Renesas Electronics IRQ Number (Inherent Priority) IRQ Name Description ● BLE_GROSSTGTIM_IRQn: Gross Target Timer interrupt generated when Gross Target timer expired. The timer resolution is 16 times 625 μs base time reference ● BLE_CSCNT_IRQn: 625 μs base time reference interrupt, available in active modes ● BLE_SLP_IRQn: End of Sleep mode interrupt ● BLE_ERROR_IRQn: Error interrupt, generated when undesired behavior or bad programming occurs in the BLE Core ● BLE_RX_IRQn: Receipt interrupt at the end of each received packets ● BLE_EVENT_IRQn: End of Advertising/Scanning/Connection events interrupt ● BLE_CRYPT_IRQn: Encryption/Decryption interrupt, generated when AES and/or CCM processing is finished ● BLE_SW_IRQn: SW triggered interrupt, generated on SW request 2 UART_IRQn UART interrupt. 3 UART2_IRQn UART2 interrupt. 4 I2C_IRQn I2C interrupt. 5 SPI_IRQn SPI interrupt. 6 ADC_IRQn Analog-Digital Converter interrupt. 7 KEYBRD_IRQn Keyboard interrupt. 8 BLE_RF_DIAG_IRQn Baseband or Radio Diagnostics Interrupt. Triggered by internal events of the Radio or Baseband selected by the BLE_RF_DIAGIRQ_REG. For Debug purposes only. 9 RF_CAL_IRQn RF Calibration Interrupt. 10 GPIO0_IRQn GPIO interrupt through debounce. 11 GPIO1_IRQn GPIO interrupt through debounce. 12 GPIO2_IRQn GPIO interrupt through debounce. 13 GPIO3_IRQn GPIO interrupt through debounce. 14 GPIO4_IRQn GPIO interrupt through debounce. 15 SWTIM_IRQn Timer0/2 interrupt. 16 WKUP_QUADEC_IRQn Combines the Wake-up Capture Timer interrupt, the GPIO interrupt, and the QuadDecoder interrupt. 17 TIM1_IRQn Timer1 interrupt. 18 RTC_IRQn Real Time Clock interrupt. 19 DMA_IRQn DMA interrupt. 20 XTAL32RDY_IRQn XTAL32M settling ready interrupt. Interrupt priorities are programmable by the Arm Cortex-M0+. The lower the priority number, the higher the priority level. The priority level is stored in a byte-wide register, which is set to 0x0 at reset. Interrupts with the same priority level follow a fixed priority order using the interrupt number listed in Table 34 (a lower interrupt number has a higher priority level). |
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