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DA14530 Datasheet(PDF) 55 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 55 Page - Renesas Technology Corp |
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55 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 55 of 332 © 2021 Renesas Electronics ● The design is configured to respond to exceptions (for example, interrupts) as soon as possible (minimum 15 clock cycles) ● Non maskable interrupt (NMI) input for safety critical systems ● Easy to use and C friendly. There are only two modes, Thread mode and Handler mode. The whole application, including exception handlers, can be written in C without any assemblers ● Built-in System Tick timer for OS support. A 24-bit timer with a dedicated exception type is included in the architecture, which the OS can use as a tick timer or as a general timer in other applications without an OS ● SuperVisor Call (SVC) instruction with a dedicated SVC exception and Pendable SuperVisor service (PendSV) to support various operations in an embedded OS ● Architecturally defined sleep modes and instructions to enter sleep. The sleep features allow power consumption to be reduced dramatically. Defining sleep modes as an architectural feature makes porting of software easier because the sleep modes are entered by specific instructions rather than implementation defined control registers ● Fault handling exception to catch various sources of errors in the system ● Support for 21 interrupts ● Little endian memory support ● Wake-up Interrupt Controller (WIC) to allow the processor to be powered down during sleep, while interrupt sources are still allowed to wake up the system ● Halt mode debug allows the processor activity to stop completely so that register values can be accessed and modified. No overhead in code size and stack memory size ● CoreSight technology allows memories and peripherals to be accessed from the debugger without halting the processor ● Supports Serial Wire Debug (SWD) connections. The SWD protocol can handle the same debug features as the JTAG, but it only requires two wires and is already supported by a number of debug solutions from various tools vendors ● Four (4) hardware breakpoints and two (2) watch points ● Breakpoint instruction support for an unlimited number of software breakpoints ● Programmer’s model similar to the ARM7TDMI processor. Most existing Thumb code for the ARM7TDMI processor can be reused. This also makes it easy for ARM7TDMI users, as there is no need to learn a new instruction set. 6.2 Architecture 6.2.1 Interrupts This section lists all 21 interrupt lines, except the NMI interrupt, and describes their sources and functionality. The overview of the interrupts is illustrated in Table 34. Table 34: Interrupt List IRQ Number (Inherent Priority) IRQ Name Description 0 BLE_WAKEUP_LP_IRQn Wake up the system from Low Power (Extended Sleep) interrupt from BLE. 1 BLE_GEN_IRQn BLE Interrupt. Sources: ● BLE_FINETGTIM_IRQn: Fine Target Timer interrupt generated when Fine Target timer expires. The timer resolution is 625 μs base time reference |
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