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DA14530 Datasheet(PDF) 54 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 54 Page - Renesas Technology Corp |
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54 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 54 of 332 © 2021 Renesas Electronics 6 Arm Cortex-M0+ 6.1 Introduction The Arm Cortex-M0+ processor is a 32-bit Reduced Instruction Set Computing (RISC) processor with a von Neumann architecture (single bus interface). It uses an instruction set called Thumb, which was first supported in the ARM7TDMI processor, but it also uses several newer instructions from the Armv6 architecture and a few instructions from the Thumb-2 technology. Thumb-2 technology extends the previous Thumb instruction set to allow all operations to be carried out in one CPU state. The instruction set in Thumb-2 includes both 16-bit and 32-bit instructions; most instructions generated by the C compiler use the 16-bit instructions, and the 32-bit instructions are used when the 16-bit version cannot carry out the required operations. This results in high code density and avoids the overhead of switching between two instruction sets. In total, the Cortex-M0+ processor supports only 56 base instructions, although some instructions can have more than one form. Although the instruction set is small, the Cortex-M0+ processor is highly capable because the Thumb instruction set is highly optimized. Academically, the Cortex-M0+ processor is classified as load-store architecture, as it has separate instructions for reading and writing to memory, and instructions for arithmetic or logical operations that use registers. It has a two-stage pipeline (fetch+predecode and decode+execute) as opposed to its predecessor (Cortex-M0) that has a three-stage pipeline (fetch, decode, and execute). A simplified block diagram of the Cortex-M0+ is shown in Figure 14. Figure 14: Arm Cortex-M0+ Block Diagram Features ● Thumb instruction set: highly efficient, of high code density, and able to execute all Thumb and Thumb-2 instructions ● High performance: up to 0.9 DMIPS/MHz (Dhrystone 2.1) with fast multiplier ● Built-in Nested Vectored Interrupt Controller (NVIC): this makes interrupt configuration and coding of exception handlers easy. When an interrupt request is taken, the corresponding interrupt handler is executed automatically without the need to determine the exception vector in software ● Interrupts can have four different programmable priority levels and the NVIC automatically handles nested interrupts |
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