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DA14530 Datasheet(PDF) 50 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 50 Page - Renesas Technology Corp |
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50 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 50 of 332 © 2021 Renesas Electronics 5 Reset 5.1 Introduction The DA14530 comprises a reset (RST) pad which is active high. It contains an RC filter with a resistor of 465 kΩ and a capacitor of 3.5 pF to suppress spikes. It also contains a 25 kΩ pull-down resistor. This pad should be driven externally by a field-effect transistor (FET) or a single button connected to VBAT. The typical latency of the RST pad is in the range of 2 µs. Features ● RC spike filter on RST to suppress external spikes (465 kΩ, 3.5 pF) ● Three different reset lines (SW, HW, and POR) ● Latching the cause of a reset operation (RESET_STAT_REG) ● Configurable POR circuitry ARM SYS_CTRL_REG[SW_RESET] Debugger APB16 WATCHDOG WDOG_reset NMI HW_RESET AIRCR[SYSRESETREQ] SWDIO SWDCLK SWDAP HW_RESET PWR ON RESET DEBUGGER_ENABLE SW_RESET POR_PIN_REG[PIN_SELECT] POR Timer RST/P0_0 POR_TIMER_REG 0x00 HWR_CTRL_REG[DISABLE_HWR] POR_VDD POR_HIGH POR_LOW WATCHDOG_CTRL_REG[NMI_RST] P0_x n Low-Pass Filter n Figure 12: Reset Block Diagram 5.2 Architecture 5.2.1 POR, HW, and SW Reset There are three main reset signals in the DA14530: ● The Power-On Reset (POR): it is optional triggered by a GPIO set as the POR source with a selectable polarity and/or the RST pad (P0_0) after a programmable time delay ● The HW reset: it is optional triggered by the RST pad (P0_0) when it becomes active for a short period of time (less than the programmable delay for POR) ● The SW reset: it is triggered by writing the SYS_CTRL_REG[SW_RESET] bit The POR signal is generated: ● Internally and will release the system’s flip flops as soon as the VDD, VBAT_HIGH, and VBAT_LOW voltages crossed the specified thresholds ● Externally by a POR source (RST pad multiplexed on a GPIO or P0_0 configured as RST pin) The HW reset can also be automatically activated when the system wakes up from the Extended or Deep Sleep mode by programming the bit PMU_CTRL_REG[RESET_ON_WAKEUP]. The POR and the HW reset basically run the cold start-up sequence and the BootROM code is executed. |
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