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DA14530 Datasheet(PDF) 48 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 48 of 332 © 2021 Renesas Electronics If the "Boot from Specific" flag is not programmed, the system should continue with scanning the different serial interfaces to identify whether a device is connected to it. After OTP is disabled, six steps as described in Table 32 are performed. Before using the UART, the XTAL32M clock is enabled. All boot steps are protected by a timeout. Read and Prog. DMA length Start copy of OTP to SRAM Copy done? Remap SysRAM to addr 0x00 and SW reset ARM is polling OTPC_STAT_REG Boot End No Is App programmed ? Read OTP “Application Flags” Magic Number identified Boot Start Default clock is RC32K Length Register will be automatically read by the OTP controller after wake up Initialize Peripheral Devices Download Code to SRAM Endless loop Enable OTP Boot specific flag = 0xAA? Read serial configuration Configure SPI pins Yes Disable OTP Disable OTP Yes Yes No Disable OTP Execute Configuration Script Boot Step 1 (ext SPIM) Boot Step 2 ( 1w UART-1) Fail Success Boot Step 3 (1w UART-2) Success Fail Boot Step 4 (2w UART) Success Fail Boot Step 5 (ext SPIS) Success Fail Boot Step 6 (I2C) Success Fail Fail Yes Boot from UART Dis_JTAG= FALSE Dis_JTAG=TRUE Flag should be updated while CS execution Switch to RC32MHz Enabled already by PWR FSM Fail Boot from ext SPIS Success Fail, Goto Boot Step 1 All Boot Steps protected by a Timeout Switch to XTAL32M before using UART Switch back to RC32M Leaving Booter with RC32M always! Initialize UART baudrate @ 115200 No Enable JTAG P0_5 for WLCSP17 P0_10 for MSTQFN24 XTAL32M OK No Yes Switch to XTAL32M Enable JTAG Dis_JTAG= TRUE Dis_JTAG= FALSE Figure 11: BootROM Sequence The one-wire UART boot capability the same as for a 2-wire UART booting except that the Booter SW controls the pin direction before sending or receiving information. |
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