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DA14530 Datasheet(PDF) 47 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 47 Page - Renesas Technology Corp |
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47 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 47 of 332 © 2021 Renesas Electronics # Command Type Description 5 UART STX timeout value One 32-bit word which is equal to 0x8XXXXXXX. The XXXXXXX is used to program the selected STX timeout in multiples of 100 µs. So, for example, 0x80000028 is 40 × 100 µS = 4 ms. 6 SPI Clock value 0xA0000000 This value overwrites the default 2-MHz clock speed of the SPI boot path and sets it to 32 MHz. The Booter stops processing the CS once it encounters an empty OTP value (0xFFFFFFFF). This way, no more processing time is spent to check the rest and it is possible to add new entries later, for example, to patch/update previous entries. An example describing the format of the configuration script is presented in Table 31. Table 31: CS Example Words Even Words Odd Words Description 0-1 0xA5A5A5A5 0x80000028 Start command of the CS Script, followed by STX timeout value of 4 ms (40 × 100 µs) 2-3 <Address> <Value> Booter automatically writes the <Value> to the <Address> 4-5 0x90000301 <Value> Three calibration values stored during production testing. SDK should know what this is for. 6-7 <Value> <Value> 8-9 <Address> <Value> Booter automatically write the <Value> to the <Address> 10-11 <Address> <Value> Booter automatically write the <Value> to <Address> 12-13 0x90000402 <Value1> Four calibration values stored during production testing. SDK should know what this is for. 14-15 <Value2> <Value3> Calibration value stored during production testing. SDK should know what this is for. 16-17 <Value4> 0x70000000 Disable SWD 18-19 0xFFFFFFFF (don’t care) Booter stops running the CS after an empty entry, so anything after this is "don’t care". 4.5 BootROM Sequence The booting process of the DA14530 is presented in Figure 11. The Booter is always executed when a POR or a HW Reset occurs, or the RESET_ON_WAKEUP feature is configured. The booter will start executing with the RC32M clock, to speed up its execution. To access the OTP, VBAT needs to be set at ≥ 1.8 V. After the OTP is operational, the Booter initializes the UART baud rate at 115.2 kHz, and the CS (section 4.4.2) is enabled to be executed. After the CS has been executed, the Booter has to decide whether the device is in Development or Normal mode by reading the two words indicated as application flags in the OTP. The OTP image is copied into RAM starting at address 0x0 by the Booter. In Development mode, the "Boot from Specific" flag will be evaluated. If this flag is programmed, new pin locations for booting from an external SPI slave to make DA14530 an SPI Master will be set allowing for booting from a different pin configuration than the default one, so that the system can boot from an external FLASH using the development mode. The details of the configuration are presented in section 4.4.1. If this path is entered, the system will always try to boot from UART so that the SPI Flash can be updated if needed. Any of the three UART configurations specified in Table 32 can be selected by writing bits [31:24] at the "Boot specific config" field in the OTP header. If booting from SPI Flash fails, the Booter will jump back to the normal scan sequence of the peripheral devices. |
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