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DA14530 Datasheet(PDF) 43 Page - Renesas Technology Corp

Part # DA14530
Description  Low Power Bluetooth 5.1 SoC
Download  333 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA14530 Datasheet(HTML) 43 Page - Renesas Technology Corp

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DA14530
Low Power Bluetooth 5.1 SoC
Final
Datasheet
Revision 3.4
21-Dec-2021
CFR0011-120-00
43 of 332
© 2021 Renesas Electronics
around 865 µs. If RAM has been retained, running software means application; if not then the Booter
will be started.
Figure 8: Wake-Up from extended/deep sleep
A GPIO trigger will have to go through the wake up controller first, which requires 7 RCX clock cycles
before it is allowed to trigger the PMU and have the state machine running. Even after all power rails
are done, switching the system clock from RCX into RC32M (so software stars running) takes 3.5
RCX clock cycles (indicated in state=RUNNING:SWITCH) in the figure above.
If the system wakes up from an internal timer running at the RCX clock, then the WokenUp signal will
be asserted 6 RCX clock cycles after the timer generates the interrupt (i.e ~400usec).
4.3.1
Go-to-Sleep and Refresh Bandgap
The sleep state disables the power-consuming blocks and triggers the "hold mode" for the bandgap
referenced voltages. After a certain amount of time (sleep refresh counter), these "hold" voltages
need to be refreshed. The lower loop of the FSM in Figure 6 enables the bandgap, refreshes the
voltages, checks for BOD events via the POR circuits and if ok, resets the refresh timer and goes
back to sleep. This is an autonomous cycle led by hardware until the system is woken up by a wake-
up event. The refresh timer can be configured by setting the PMU_SLEEP_REG
[BG_REFRESH_INTERVAL] bit field (1 LSB = 64 × 32 kHz clock cycles). The go-to-sleep and the
bandgap refresh sequence is shown in Figure 9.
Figure 9: Go-to-Sleep and Bandgap Refresh
4.4
OTP Memory Layout
The OTP memory has to be programmed according to a specific layout, which structures information
to be easily accessible from the BootROM code as well as the actual application. An overview of the
layout scheme is presented in Figure 10.


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