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DA14530 Datasheet(PDF) 42 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 42 Page - Renesas Technology Corp |
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42 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 42 of 332 © 2021 Renesas Electronics When POR_HIGH is masked, its status remains available, but it will not generate a reset. POR_HIGH can be also disabled by the following setting: o POWER_CTRL_REG[POR_VBAT_HIGH_DISABLE] = 0x1 When POR_ HIGH is disabled, its status becomes unavailable. 4.3 HW FSM (Power-up, Wake-up, and Go-to-Sleep) The HW Finite State Machine (FSM) responsible for the power-up, wake-up, and go-to-sleep processes of the system is presented in Figure 6. RESET_N=0 Bandgap Enable LDO_CORE Enable LDO_CORE = OK BootROM (SW) starts Running Sleep Bandgap Sleep Referent Voltage Tracking Go To Sleep Bandgap refresh Wake Up Bandgap = OK Figure 6: Power-Up/Wake-Up/Sleep FSM Diagram The details of the wake-up, and sleep sequences of the FSM for the different modes are described in the following paragraphs. To wake up from hibernation, one of the designated GPIOs has to be triggered. A synchronization phase of at least 3 RC32KHz cycles is needed before the bandgap is enabled and the clock switches in fast mode. In the next step the LDO_CORE is enabled and then the system reset can be released for the Booter to start running. The total time needed to wake up the system from hibernation up until booter software starts running is around 180 µs. Figure 7: Power up/Wake-Up from hibernation In the wake-up sequence from deep or extended sleep using a GPIO toggle, the timing is presented in Figure 8. The total time which is needed to power up the system up until software starts running is |
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