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DA14530 Datasheet(PDF) 41 Page - Renesas Technology Corp

Part # DA14530
Description  Low Power Bluetooth 5.1 SoC
Download  333 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA14530 Datasheet(HTML) 41 Page - Renesas Technology Corp

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DA14530
Low Power Bluetooth 5.1 SoC
Final
Datasheet
Revision 3.4
21-Dec-2021
CFR0011-120-00
41 of 332
© 2021 Renesas Electronics
4.2.2.3
VDD Level in Hibernation
While in Hibernation, the Always On domain (PD_AON) is supplied by a clamp. Since the reference
is not enabled, the actual voltage supplied by the clamp is depending on the load and temperature.
To ensure proper operation of the PD_AON across the application operating temperature range and
load, it is recommended to configure the voltage level of the VDD_Clamp using
POWER_AON_CTRL_REG[LDO_RET_TRIM] according to the following table:
Table 27: VDD_Clamp recommended settings over temperature and load
Temperature Range
0kB retained RAM
48kB retained RAM
-40oC to +40oC
0xE
0xD
-40oC to +60oC
0xD
0xC
-40oC to +85oC
0xB
0xA
4.2.2.4
Retainable Registers
When the system enters one of the sleep modes, some registers need to retain their values even
though their power domain might be shut down. These special retainable registers and their power
domains are described in Table 28.
Table 28: Retainable Registers
Power Domains
Retainable Registers
PD_SYS
OTPC_MODE_REG
OTPC_TIM1_REG
OTPC_TIM2_REG
OTPC_AHBADR_REG
OTPC_CELADR_REG
OTPC_NWORDS_REG
DEBUG_REG
PD_RAD
BLE_CNTL2_REG
RF_ADCI_DC_OFFSET_REG
RF_ADCQ_DC_OFFSET_REG
RF_DC_OFFSET_RESULT_REG
RF_DC_OFFSET_FULL_RES_REG
RF_DC_OFFSET_MPAR_RES0/1/2/3_REG
4.2.3
Programming
Initial voltage at VBAT has to be above 1.8 V to allow the OTP to be read and mirrored. Software can
disable LDO_LOW to reduce quiescent current. The following register settings are required to
accomplish this:
o
POWER_CTRL_REG[LDO_LOW_CTRL_REG] = 0x1
If voltage drops below 1.75 V, POR_HIGH must be masked in order to prevent unnecessary resets.
Note that OTP reads cannot be performed after this point. Masking POR_HIGH is done by the
following setting:
o
POWER_AON_CTRL_REG[POR_VBAT_HIGH_RST_MASK] = 0x1


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