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DA14530 Datasheet(PDF) 40 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 40 Page - Renesas Technology Corp |
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40 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 40 of 332 © 2021 Renesas Electronics Table 26: Power Modes, Digital Power Domains, Clocks, and Wake-up triggers Power Mode Digital Power Domains LDOs and VDD Level Clock Availability RAM Wake Up from Active or Sleep (WFI) PD_AON = ON PD_SLP = ON PD_SYS = ON PD_TIM = OPTIONAL PD_RAD = OPT VDD = 0.9 V LDO_LOW = OFF LDO_CORE = ON, Active (0.9 V) VDD_Clamp = OFF LDO_RADIO = Programmable All SysRAM1 = ON (Application) SysRAM2 = optionally retained SysRAM3 = ON (Stack Data) Extended Sleep (with or without OTP) PD_AON = ON PD_SLP = ON PD_SYS = OFF PD_TIM = OPTIONAL PD_RAD = OFF VDD = 0.75 V LDO_LOW = OFF LDO_CORE = ON, in retain mode (0.75 V) VDD_Clamp = OFF LDO_RADIO = OFF RCX or XTAL32K SysRAMx =optionally retained (typically only SysRAM1 is retained) ● RTC alarm ● Timer1 ● BLE sleep timer Deep Sleep PD_AON = ON PD_SLP = ON PD_SYS = OFF PD_TIM = OPTIONAL PD_RAD = OFF VDD = 0.75 V LDO_LOW = OFF LDO_CORE = ON, in retain mode (0.75 V) VDD_Clamp = OFF LDO_RADIO = OFF RCX or XTAL32K SysRAMx = optionally retained (Typically OFF) ● from any GPIOs ● RTC alarm ● Timer1 Hibernation PD_AON = ON PD_SLP = OFF PD_SYS = OFF PD_TIM = OFF PD_RAD = OFF VDD = ~0.75 V LDO_LOW = OFF LDO_CORE = OFF VDD_Clamp = ~0.75 V LDO_RADIO = OFF No Clocks SysRAMx =optionally retained Wake up from P0_1, P0_2, P0_3, P0_4, P0_5 |
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