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DA14530 Datasheet(PDF) 4 Page - Renesas Technology Corp

Part # DA14530
Description  Low Power Bluetooth 5.1 SoC
Download  333 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA14530 Datasheet(HTML) 4 Page - Renesas Technology Corp

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DA14530
Low Power Bluetooth 5.1 SoC
Final
Datasheet
Revision 3.4
21-Dec-2021
CFR0011-120-00
4 of 332
© 2021 Renesas Electronics
5.2.1
POR, HW, and SW Reset.................................................................................... 50
5.2.2
POR Functionality................................................................................................ 51
5.2.2.1
POR Timer Clock............................................................................. 52
5.2.2.2
RST Pad .......................................................................................... 52
5.2.2.3
POR from GPIO............................................................................... 52
5.2.3
POR Timing Diagram........................................................................................... 52
5.2.4
POR Considerations ............................................................................................ 53
5.3
Programming....................................................................................................................... 53
6
Arm Cortex-M0+........................................................................................................................... 54
6.1
Introduction ......................................................................................................................... 54
6.2
Architecture ......................................................................................................................... 55
6.2.1
Interrupts.............................................................................................................. 55
6.2.2
System Timer (systick) ........................................................................................ 57
6.2.3
Wake-Up Interrupt Controller............................................................................... 57
6.3
Programming....................................................................................................................... 57
7
AMBA Bus .................................................................................................................................... 58
7.1
Introduction ......................................................................................................................... 58
7.2
Architecture ......................................................................................................................... 58
7.3
Programming....................................................................................................................... 59
8
Memory Map................................................................................................................................. 60
9
Memory Controller ...................................................................................................................... 62
9.1
Introduction ......................................................................................................................... 62
9.2
Architecture ......................................................................................................................... 62
9.2.1
Arbitration ............................................................................................................ 62
10 Clock Generation......................................................................................................................... 64
10.1 Clock Tree........................................................................................................................... 64
10.1.1
General Clock Constraints................................................................................... 66
10.2 Crystal Oscillators ............................................................................................................... 66
10.2.1
Frequency Control (32 MHz Crystal) ................................................................... 66
10.2.2
Automated Trimming and Settling Notification .................................................... 67
10.3 RC Oscillators ..................................................................................................................... 68
10.3.1
Frequency Calibration.......................................................................................... 69
11 OTP Controller ............................................................................................................................. 70
11.1 Introduction ......................................................................................................................... 70
11.2 Architecture ......................................................................................................................... 70
11.2.1
OTP Accessing Considerations........................................................................... 72
11.3 Programming....................................................................................................................... 72
12 DMA Controller ............................................................................................................................ 73
12.1 Introduction ......................................................................................................................... 73
12.2 Architecture ......................................................................................................................... 73
12.2.1
DMA Peripherals.................................................................................................. 73
12.2.2
Input/Output Multiplexer ...................................................................................... 74
12.2.3
DMA Channel Operation...................................................................................... 74
12.2.4
DMA Arbitration ................................................................................................... 75
12.2.5
Freezing DMA Channels ..................................................................................... 76


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