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DA14530 Datasheet(PDF) 38 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 38 Page - Renesas Technology Corp |
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38 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 38 of 332 © 2021 Renesas Electronics VBAT VBAT XTAL1 XTAL2 32MHz Bandgap Isupply=50uA XTAL 32M GP ADC Isup=50uA Typ 3.0V (1.8 ... 3.3V) Typ 1.1V (1.1 ... 3.3V) LDO GPADC 1mA LDO XTAL 1mA 0.9V 0.9V RADIO XTAL 32k 0.75V ... 0.9V LDO VDD 6mA VDD VDD DCORE Temp sensor RC 32M RCX LNA/Mix/ TIA/IFF/ ADC/DACs LDO RF IF 3...8mA 0.9V DCO/LO/ DIV LDO RF LO 2mA 0.9V LDO LOW RET POR LOW >0.95V POR HIGH >1.62V OTP Memory >1.8V VDD Clamp POR_VDD RC32kHz Nx GPIO PORTS XTAL1 XTAL2 32MHz Bandgap XTAL 32M 2.3V - 3.3V 2.3V - 3.3V LDO XTAL 0.9V RADIO XTAL 32k 0.75V ... 0.9V ret mode VDD VDD DCORE RC 32M RCX LDO LOW POR HIGH <1.66V OTP Memory >1.8V VDD Clamp POR_VDD RC32kHz LDO CORE Always enabled Enabled by HW FSM Enabled by Software 32k_n 32k_p GP ADC LDO GPADC 0.9V 0.9V RF Blocks LDO RF RF Blocks LDO RF 0.9V 0.9V RF Blocks LDO RF ret mode Temp sensor POR LOW <1.00V Figure 4: Power Management Unit: Bypass Configuration 4.2.2.1 Digital Power Domains The DA14530 supports a number of digital power domains that can be turned on and off by software (Figure 5). Some of the blocks contain registers that can retain their values even if the digital power domain where they reside is powered off. RAM cells can retain their contents independently from the digital power domains state. Arm Cortex M0+ POR HIGH POR LOW XTAL 32.768 kHz XTAL 32 MHz RAM Ctrl LDO LOW BLE 5.1 MAC GPIO Multiplexing SPI I2C General Purpose Registers TIMER0/2 QuadRature Decoder (x3) Keyboard Scanner 4-ch 10-bit ADC Temperature sensor Radio Tranceiver LDO CORE RF LDO Digital PHY RFCU UART/UART2 CLOCK GEN RAM 48 kB DMA Engine OTP Ctrl OTP 32 kB ROM Ctrl ROM 144 kB AMBA AHB AMBA APB Sleep Domain (PD_SLP) Always On Domain (PD_AON) System Domain (PD_SYS) Radio Domain (PD_RAD) Analog/RF RTC Timers Domain (PD_TIM) TIMER1 Figure 5: Digital Power Domains The list of blocks residing in each one of the digital power domains is presented in Table 25. |
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