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DA14530 Datasheet(PDF) 37 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 37 Page - Renesas Technology Corp |
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37 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 37 of 332 © 2021 Renesas Electronics Wake-Up Timer. This timer captures external events and it can be used on any of the GPIO ports as a wake-up trigger based on a programmable number of external events. Quadrature Decoder. This block decodes the pulse trains from a rotary encoder to provide the step and the direction of a movement of an external device. Three axes (X, Y, and Z) are supported. The block also supports an edge counting mode which enables counting positive or negative edges on the selected GPIOs. Keyboard Controller. This circuit enables the reading and debouncing of a programmable number of GPIOs and generates an interrupt upon a configurable action. AHB/APB Bus. This block implements the AMBA Lite version of the AHB and APB specifications. Power Management. The power management circuit is equipped with several low-dropout regulators (LDOs) that can be turned on/off via software. A more detailed description of each component of the DA14530 is presented in the following sections. 4.2 Power Management Unit 4.2.1 Introduction The DA14530 has an integrated power management unit (PMU) which comprises a VDD_Clamp, a POR circuitry and various LDOs. The system diagram of the integrated PMU is shown in Error! Reference source not found.. Features ● Active and sleep mode LDOs ● Low BOM and use of small external components 4.2.2 Architecture The PMU integrates two internal VBAT and a VDD power rail. ● VBAT with a voltage range of minimum 2.3 V up to 3.3 V. The minimum voltage is dictated by the capability of OTP being programmed in the field. If OTP programming is not required, then the minimum battery voltage will be 1.8V which is needed to be able to read from the OTP memory ● The internal VDD power rail supplies the digital power domains (refer to section 4.2.2.1 for the details) The PMU block diagram is presented in Figure 4. Note that, GPIOs supply follows the battery voltage. |
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