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DA14530 Datasheet(PDF) 36 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 36 Page - Renesas Technology Corp |
36 / 333 page ![]() DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 36 of 332 © 2021 Renesas Electronics 4 System Overview 4.1 Internal Blocks The DA14530 contains the following blocks: Arm Cortex-M0+ CPU with Wake-up Interrupt Controller (WIC). This processor provides 0.9 dMIPS/MHz and is used for assisting the BLE protocol implementation, for providing processing power for calculations or data fetches required by applications, and for housekeeping, including controlling the power scheme of the system. BLE core. This is the baseband hardware accelerator for the BLE protocol. ROM. This 144-kB ROM contains the BLE protocol stack and the boot code sequence. OTP. This 32-kB OTP memory array is used to store application code and BLE profiles. It also contains the system configuration and calibration data. System SRAM (SysRAM). This 48-kB SysRAM is primarily used to mirror the program code from the OTP when the system wakes/powers up. It also serves as a Data RAM for intermediate variables and various data that the protocol requires. It can be used as an extra memory space for the BLE TX and RX data structures (Exchange RAM). The SysRAM cells can not only be retained during sleep modes but also be completely switched off during active mode if not needed. UART and UART2. The serial interface of the UART implements hardware flow control while UART2 does not. Both UARTs feature FIFOs with depths of 16 bytes each. SPI. This is the serial peripheral interface (SPI) with master/slave capability and it has a separate FIFOs for RX and TX of two 16-bit words each. I2C. This Master/Slave I2C interface is used for sensors and/or host Micro-Controllers Units (MCUs) communication. It comprises a 32-place 9-bit deep FIFO. General Purpose (GP) ADC. This 10-bit analog-to-digital converter (ADC) has four external input channels (GPIOs) and internal channels for reading die temperature, the battery voltage, and other internal analog nodes. Radio Transceiver. This block implements the RF part of the BLE protocol. Clock Generator. This block is responsible for clocking the system. It contains two XTAL oscillators, one running at 32 MHz (XTAL32M) and used for the active mode of the system and the other running at 32.768 kHz (XTAL32K) and used for the sleep modes of the system. There are also three RC oscillators available: a 32 MHz oscillator (RC32M) with low precision (> 500 ppm), a 32 kHz oscillator (RC32K) with low precision (> 500 ppm), and a ~15 kHz oscillator (RCX) with high precision (< 500 ppm). The RCX oscillator can be used as a sleep clock to replace the XTAL32K oscillator to further improve the power dissipation of the system while reducing the bill of materials. The RC32M oscillator is used to provide a clock to mirror the OTP code into the SysRAM while the XTAL32M oscillator is settling directly after power/wake up. This clock is also used to run the Booter at power- up. An external digital clock can be used as a sleep clock to replace the XTAL32K or the RCX oscillator. Timers. This block contains three timers: ● A 16-bit general purpose timer (Timer0) with two pulse width modulation (PWM) signals (PWM1 is inverted to PWM0) ● A 11-bit timer (Timer1) with two capture channels ● A 14-bit timer (Timer2) which controls six PWM signals that all have the same frequency, but each has a configurable duty cycle Real Time Clock (RTC). This hardware controller supports the complete time of day clock: 12/24 hours, minutes, seconds, milliseconds, and hundredths of a millisecond. It includes a configurable alarm function and can be programmed to generate an interrupt on any event, like a rollover of month, day, hour, minute, second, or hundredths of a millisecond. |
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