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87C749 Datasheet(PDF) 16 Page - NXP Semiconductors

Part # 87C749
Description  80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

87C749 Datasheet(HTML) 16 Page - NXP Semiconductors

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Philips Semiconductors
Preliminary specification
83C749/87C749
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
1998 Apr 23
16
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C749 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
Table 3. Implementing Program/Verify Modes
OPERATION
SERIAL CODE
P0.1 (PGM/)
P0.2 (VPP)
Program user EPROM
296H
–*
VPP
Verify user EPROM
296H
VIH
VIH
Program key EPROM
292H
–*
VPP
Verify key EPROM
292H
VIH
VIH
Program security bit 1
29AH
–*
VPP
Program security bit 2
298H
–*
VPP
Verify security bits
29AH
VIH
VIH
NOTE:
*
Pulsed from VIH to VIL and returned to VIH.
EPROM PROGRAMMING AND VERIFICATION
Tamb = 21°C to +27°C, VCC = 5V ±10%, VSS = 0V
SYMBOL
PARAMETER
MIN
MAX
UNIT
1/tCLCL
Oscillator/clock frequency
1.2
6
MHz
tAVGL1
Address setup to P0.1 (PROG–) low
10
µs + 24tCLCL
tGHAX
Address hold after P0.1 (PROG–) high
48tCLCL
tDVGL
Data setup to P0.1 (PROG–) low
38tCLCL
tDVGL
Data setup to P0.1 (PROG–) low
38tCLCL
tGHDX
Data hold after P0.1 (PROG–) high
36tCLCL
tSHGL
VPP setup to P0.1 (PROG–) low
10
µs
tGHSL
VPP hold after P0.1 (PROG–)
10
µs
tGLGH
P0.1 (PROG–) width
90
110
µs
tAVQV2
VPP low (VCC) to data valid
48tCLCL
tGHGL
P0.1 (PROG–) high to P0.1 (PROG–) low
10
µs
tSYNL
P0.0 (sync pulse) low
4tCLCL
tSYNH
P0.0 (sync pulse) high
8tCLCL
tMASEL
ASEL high time
13tCLCL
tMAHLD
Address hold time
2tCLCL
tHASET
Address setup to ASEL
13tCLCL
tADSTA
Low address to address stable
13tCLCL
NOTES:
1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP).
2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.


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