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87C552 Datasheet(PDF) 5 Page - NXP Semiconductors

Part # 87C552
Description  80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

87C552 Datasheet(HTML) 5 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
1998 May 01
5
PIN DESCRIPTION
PIN NO.
MNEMONIC
PLCC
QFP
TYPE
NAME AND FUNCTION
VDD
2
72
I
Digital Power Supply: +5V power supply pin during normal operation, idle and
power-down mode.
STADC
3
74
I
Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
be started by software).
PWM0
4
75
O
Pulse Width Modulation: Output 0.
PWM1
5
76
O
Pulse Width Modulation: Output 1.
EW
6
77
I
Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0-P0.7
57-50
58-51
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input
the code byte during programming and to output the code byte during verification.
P1.0-P1.7
16-23
10-17
I/O
Port 1: 8-bit I/O port. Alternate functions include:
16-21
10-15
I/O
(P1.0-P1.5): Quasi-bidirectional port pins.
22-23
16-17
I/O
(P1.6, P1.7): Open drain port pins.
16-19
10-13
I
CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
20
14
I
T2 (P1.4): T2 event input.
21
15
I
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
22
16
I/O
SCL (P1.6): Serial port clock line I2C-bus.
23
17
I/O
SDA (P1.7): Serial port data line I2C-bus.
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
P2.0-P2.7
39-46
38-42,
45-47
I/O
Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also
used to input the upper order address during EPROM programming and verification. A8 is
on P2.0, A9 on P2.1, through A12 on P2.4.
P3.0-P3.7
24-31
18-20,
23-27
I/O
Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
24
18
RxD(P3.0): Serial input port.
25
19
TxD (P3.1): Serial output port.
26
20
INT0 (P3.2): External interrupt.
27
23
INT1 (P3.3): External interrupt.
28
24
T0 (P3.4): Timer 0 external input.
29
25
T1 (P3.5): Timer 1 external input.
30
26
WR (P3.6): External data memory write strobe.
31
27
RD (P3.7): External data memory read strobe.
P4.0-P4.7
7-14
80, 1-2
4-8
I/O
Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
7-12
80, 1-2
4-6
O
CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.
13, 14
7, 8
O
CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
P5.0-P5.7
68-62,
71-64,
I
Port 5: 8-bit input port.
1
ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
RST
15
9
I/O
Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3
overflows.
XTAL1
35
32
I
Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external clock signal when an external oscillator is
used.
XTAL2
34
31
O
Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
when an external clock is used.
VSS
36, 37
34-36
I
Digital ground.
PSEN
47
48
O
Program Store Enable: Active-low read strobe to external program memory.


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