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83C752 Datasheet(PDF) 10 Page - NXP Semiconductors |
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83C752 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 24 page  Philips Semiconductors Product specification 83C752/87C752 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count 1998 May 01 10 Special Function Register Addresses Special function registers for the 8XC752 are identical to those of the 80C51, except for the changes listed below: 80C51 special function registers not present in the 8XC752 are TMOD (89), P2 (A0) and IP (B8). The 80C51 registers TH1, TL1, SCON, and SBUF are replaced with the 8XC752 registers RTH, RTL, I2CON, and I2DAT, respectively. Additional special function registers are I2CFG (D8) and I2STA (FB), ADCON (A0), ADAT (84), PWM (8E), PWMP (8F), and PWENA (FE). See Table 3. A/D Converter The analog input circuitry consists of a 5-input analog multiplexer and an A to D converter with 8-bit resolution. The conversion takes 40 machine cycles, i.e., 40 µs at 12MHz oscillator frequency. The A/D converter is controlled using the ADCON control register. Input channels are selected by the analog multiplexer through ADCON register bits 0–2. The 83C752 contains a five-channel multiplexed 8-bit A/D converter. The conversion requires 40 machine cycles (40 µs at 12MHz oscillator frequency). The A/D converter is controlled by the A/D control register, ADCON. Input channels are selected by the analog multiplexer by bits ADCON.0 through ADCON.2. The ADCON register is not bit addressable. ADCON Register MSB LSB X X ENADC ADCI ADCS AADR2 AADR1 AADR0 ADCI ADCS Operation 0 0 ADC not busy, a conversion can be started. 0 1 ADC busy, start of a new conversion is blocked. 1 0 Conversion completed, start of a new conversion is blocked. 1 1 Not possible. INPUT CHANNEL SELECTION ADDR2 ADDR1 ADDR0 INPUT PIN 0 0 0 P1.0 0 0 1 P1.1 0 1 0 P1.2 0 1 1 P1.3 1 0 0 P1.4 Position Symbol Function ADCON.5 ENADC Enable A/D function when ENADC = 1. Reset forces ENADC = 0. ADCON.4 ADCI ADC interrupt flag. This flag is set when an ADC conversion is complete. If IE.6 = 1, an interrupt is requested when ADCI = 1. The ADCI flag is cleared when conversion data is read. This flag is read only. ADCON.3 ADCS ADC start. Setting this bit starts an A/D conversion. Once set, ADCS remains high throughout the conversion cycle. On completion of the conversion, it is reset just before the ADCI interrupt flag is cleared. ADCS cannot be reset by software. ADCS should not be used to monitor the A/D converter status. ADCI should be used for this purpose. ADCON.2 AADR2 Analog input select. ADCON.1 AADR1 Analog input select. ADCON.0 AADR0 Analog input select. This binary coded address selects one of the five analog input port pins of P1 to be input to the converter. It can only be changed when ADCI and ADCS are both low. AADR2 is the most significant bit. The completion of the 8-bit ADC conversion is flagged by ADCI in the ADCON register, and the result is stored in the special function register ADAT. An ADC conversion in progress is unaffected by an ADC start. The result of a completed conversion remains unaffected provided ADCI remains at a logic 1. While ADCS is a logic 1 or ADCI is a logic 1, a new ADC START will be blocked and consequently lost. An ADC conversion in progress is aborted when the idle or power-down mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle mode. See Figure 2 for an A/D input equivalent circuit. The analog input pins ADC0-ADC4 may be used as digital inputs and outputs when the A/D converter is disabled by a 0 in the ENADC bit in ADCON. When the A/D is enabled, the analog input channel that is selected by the ADDR2-ADDR0 bits in ADCON cannot be used as a digital input. Reading the selected A/D channel as a digital input will always return a 1. The unselected A/D inputs may always be used as digital inputs. Unselected analog inputs will be floating and may not be used as digital outputs. The A/D reference inputs on the 8XC752 are tied together with the analog supply pins AVCC and AVSS. This means that the reference voltage on the A/D cannot be varied separately from the analog supply pins. AVSS must be connected to 0V and AVCC must be connected to a supply voltage between 4.5V and 5.5V. A/D measurements may be made in the range of 4.5V to 5.5V. Increasing the voltage on the A/D ground reference above 0V or reducing the voltage on the positive A/D reference below 4.5V is not permitted. |
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