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83C752 Datasheet(PDF) 8 Page - NXP Semiconductors |
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83C752 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 24 page  Philips Semiconductors Product specification 83C752/87C752 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count 1998 May 01 8 Interrupt Enable Register MSB LSB EA EAD ETI ES EPWM EX1 ET0 EX0 Position Symbol Function IE.7 EA Global interrupt disable when EA = 0 IE.6 EAD A/D conversion complete IE.5 ETI Timer I IE.4 ES I2C serial port IE.3 EPWM PWM counter overflow IE.2 EX1 External interrupt 1 IE.1 ET0 Timer 0 overflow IE.0 EX0 External interrupt 0 Serial Communications The 8XC752 contains an I2C serial communications port instead of the 80C51 UART. The I2C serial port is a single bit hardware interface with all of the hardware necessary to support multimaster and slave operations. Also included are receiver digital filters and timer (timer I) for communication watch-dog purposes. The I2C serial port is controlled through four special function registers; I2C control, I2C data, I2C status, and I2C configuration. The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main technical features of the bus are: • Bidirectional data transfer between masters and slaves • Serial addressing of slaves • Acknowledgment after each transferred byte • Multimaster bus • Arbitration between simultaneously transmitting master without corruption of serial data on bus • With 82B715, communication distance is extended to beyond 100 feet (30M) A large family of I2C compatible ICs is available. See the I2C section for more details on the bus and available ICs. The 83C752 I2C subsystem includes hardware to simplify the software required to drive the I2C bus. This circuitry is the same as that on the 83C751. (See the 83C751 section for a detailed discussion of this subsystem). Pulse Width Modulation Output (P0.4) The PWM outputs pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler which generates the clock for the counter. The prescaler register is PWMP. The prescaler and counter are not associated with any other timer. The 8-bit counter counts modulo 255, that is from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of a compare register, PWM. When the counter value matches the contents of this register, the output of the PWM is set high. When the counter reaches zero, the output of the PWM is set low. The pulse width ratio (duty cycle) is defined by the contents of the compare register and is in the range of 0 to 1 programmed in increments of 1/255. The PWM output can be set to be continuously high by loading the compare register with 0 and the output can be set to be continuously low by loading the compare register with 255. The PWM output is enabled by a bit in a special function register, PWENA. When enabled, the pin output is driven with a fully active pull-up. That is, when the output is high, a strong pull-up is continuously applied. when disabled, the pin functions as a normal bidirectional I/O pin, however, the counter remains active. The PWM function is disabled during RESET and remains disabled after reset is removed until re-enabled by software. The PWM output is high during power down and idle. The counter is disabled during idle. The repetition frequency of the PWM is given by: fPWM = fOSC / 2 (1 + PWMP) 255 The low/high ratio of the PWM signal is PWM / (255 – PWM) for PWM not equal to 255. For PWM = 255, the output is always low. The repetition frequency range is 92Hz to 23.5kHz for an oscillator frequency of 12MHz. An interrupt will be asserted upon PWM counter overflow if the interrupt is not masked off. The PWM output is an alternative function of P0.4. In order to use this port as a bidirectional I/O port, the PWM output must be disabled by clearing the enable/disable bit in PWENA. In this case, the PWM subsystem can be used as an interval timer by enabling the PWM interrupt. |
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