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83C752 Datasheet(PDF) 7 Page - NXP Semiconductors |
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83C752 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 24 page  Philips Semiconductors Product specification 83C752/87C752 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count 1998 May 01 7 P1.X LATCH DQ CL Q READ LATCH INT. BUS WRITE TO LATCH READ PIN ALTERNATE INPUT FUNCTION VDD P1.X PIN INTERNAL PULL-UP ALTERNATE OUTPUT FUNCTION P0.X LATCH DQ CL Q READ LATCH INT. BUS WRITE TO LATCH READ PIN ALTERNATE INPUT FUNCTION P0.X PIN ALTERNATE OUTPUT FUNCTION SU00306 Figure 1. Port Bit Latches and I/O Buffers I/O Ports The I/O pins provided by the 83C752 consist of port 0, port 1, and port 3. Port 0 Port 0 is a 5-bit bidirectional I/O port and includes alternate functions on some pins of this port. Pins P0.3 and P0.4 are provided with internal pullups while the remaining pins (P0.0, P0.1, and P0.2) have open drain output structures. The alternate functions for port 0 are: P0.0 SCL – the I2C bus clock P0.1 SDA – the I2C bus data P0.4 PWM – the PWM output If the alternate functions, I2C and PWM, are not being used, then these pins may be used as I/O ports. Port 1 Port 1 is an 8-bit bidirectional I/O port whose structure is identical to the 80C51, but also includes alternate input functions on all pins. The alternate pin functions for port 1 are: P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs P1.5 INT0 - external interrupt 0 input P1.6 INT1 - external interrupt 1 input P1.7 - T0 - timer 0 external input If the alternate functions INT0, INT1, or T0 are not being used, these pins may be used as standard I/O ports. It is necessary to connect AVCC and AVSS to VCC and VSS, respectively, in order to use these pins as standard I/O pins. When the A/D converter is enabled, the analog channel connected to the A/D may not be used as a digital input; however, the remaining analog inputs may be used as digital inputs. They may not be used as digital outputs. While the A/D is enabled, the analog inputs are floating. Port 3 Port 3 is an 8-bit bidirectional I/O port whose structure is identical to the 80C51. Note that the alternate functions associated with port 3 of the 80C51 have been moved to port 1 of the 83C752 (as applicable). See Figure 1 for port bit configurations. Counter/Timer Subsystem The 8XC752 has one counter/timer called timer/counter 0. Its operation is similar to mode 2 operation on the 80C51, but is extended to 16 bits with 16 bits of autoload. The controls for this counter are centralized in a single register called TCON. A watchdog timer, called Timer I, is for use with the I2C subsystem. In I2C applications, this timer is dedicated to time-generation and bus monitoring of the I2C. In non-I2C applications, it is available for use as a fixed time-base. Interrupt Subsystem—Fixed Priority The IP register and the 2-level interrupt system of the 80C51 are eliminated. The interrupt structure is a seven-source, one-level interrupt system similar to the 8XC751. Simultaneous interrupt conditions are resolved by a single-level, fixed priority as follows: Highest priority: Pin INT0 Counter/timer flag 0 Pin INT1 PWM Timer I Serial I2C Lowest priority: ADC The vector addresses are as follows: Source Vector Address INT0 0003H TF0 000BH INT1 0013H TIMER I 001BH SIO 0023H ADC 002BH PWM 0033H Interrupt Control Registers The 80C51 interrupt enable register is modified to take into account the different interrupt sources of the 8XC752. |
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