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80C554 Datasheet(PDF) 67 Page - NXP Semiconductors |
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80C554 Datasheet(HTML) 67 Page - NXP Semiconductors |
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67 / 76 page  Philips Semiconductors Preliminary specification 80C554/83C554/87C554 80C51 8-bit microcontroller – 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP 2000 Nov 10 67 Table 11. I2C-bus interface timing All values referred to VIH(min) and VIL(max) levels; see Figure 565. I2C-BUS SYMBOL PARAMETER INPUT OUTPUT tHD;STA START condition hold time ≥ 7 tCLK > 4.0 µs1 tLOW LOW period of the SCL clock ≥ 8 tCLK > 4.7 µs1 tHIGH HIGH period of the SCL clock ≥ 7 tCLK > 4.0 µs1 tRC Rise time of SCL signals ≤ 1 µs –2 tFC Fall time of SCL signals ≤ 0.3 µs < 0.3 µs3 tSU;DAT1 Data set-up time ≥ 250 ns > 10 tCLK–tRD tSU;DAT2 SDA set-up time (before repeated START condition) ≥ 250 ns > 1 µs1 tSU;DAT3 SDA set-up time (before STOP condition) ≥ 250 ns > 4 tCLK tHD;DAT Data hold time ≥ 0 ns > 4 tCLK–tFC tSU;STA Set-up time for a repeated START condition ≥ 7 tCLK > 4.7 µs1 tSU;STO Set-up time for STOP condition ≥ 7 tCLK > 4.0 µs1 tBUF Bus free time between ≥ 7 tCLK > 4.7 µs1 tRD Rise time of SDA signals ≤ 1 µs –2 tFD Fall time of SDA signals ≤ 0.3 µs < 0.3 µs3 NOTES 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs. 3. Spikes of the SDA and SCL lines with a duration of less than 3 tCLK will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. tCLK = 1/fCLK = one oscillator clock period at pin XTAL1. For 83 ns < tCLK < 285 ns (12 MHz > fCLK > 3.5 MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. 5. These values are guaranteed but not 100% production tested. 6. See application note AN457 for external memory interface. 7. Parts are guaranteed to operate down to 0Hz. |
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