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80C554 Datasheet(PDF) 63 Page - NXP Semiconductors |
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80C554 Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 76 page  Philips Semiconductors Preliminary specification 80C554/83C554/87C554 80C51 8-bit microcontroller – 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP 2000 Nov 10 63 DEVICE SPECIFICATIONS TYPE SUPPLY VOLTAGE (V) FREQUENCY (MHz) SUPPLY VOLTAGE (V) FREQUENCY (MHz) TEMPERATURE E T TYPE MIN MAX MIN MAX MIN MAX MIN MAX TE PE TU E RANGE ( °C), Tamb P87C554 SBBD 2.7 5.5 0 8 4.5 V 5.5 V 0 16 0 to +70 P87C554 SFBD 3.0 5.5 0 8 4.5 V 5.5 V 0 16 –40 to +85 DC ELECTRICAL CHARACTERISTICS VSS, AVSS = 0 V; VDD and Tamb minimum and maximum, per device specifications table. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT IDD Supply current operating See notes 1 and 2 fOSC = 8 MHz fOSC = 16 MHz 16 32 mA IID Idle mode See notes 1 and 3 fOSC = 8 MHz fOSC = 16 MHz 4 8 mA IPD Power-down current See notes 1 and 4; 2 V < VPD < VDD max 50 µA Inputs VIL Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V VIL1 Input low voltage to EA –0.5 0.2VDD–0.3 V VIL2 Input low voltage to P1.6/SCL, P1.7/SDA5 –0.5 0.3VDD V VIH Input high voltage, except XTAL1, RST 0.2VDD+0.9 VDD+0.5 V VIH1 Input high voltage, XTAL1, RST 0.7 VDD VDD+0.5 V VIH2 Input high voltage, P1.6/SCL, P1.7/SDA5 0.7 VDD 6.0 V IIL Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 VIN = 0.45 V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 See note 6 –650 µA ±IIL1 Input leakage current, port 0, EA, STADC, EW 0.45 V < VI < VDD 10 µA ±IIL2 Input leakage current, P1.6/SCL, P1.7/SDA 0 V < VI < 6 V 0 V < VDD < 5.5 V 10 µA ±IIL3 Input leakage current, port 5 0.45 V < VI < VDD 1 µA ±IIL4 Input leakage current, ports 1, 2, 3, 4 in high impedance mode 0.45 V < Vin < VDD 10 µA Outputs VOL Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 IOL = 1.6 mA7 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 IOL = 3.2 mA7 0.4 V VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0 mA7 0.4 V VOH Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA VCC = 2.7 V VCC –0 7 V IOH = –20 µA VCC – 0.7 V VCC = 4.5 VCC –0 7 V IOH = –30 µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode, ALE, PSEN, PWM0, PWM1)8 VCC = 2.7 V IOH = –3.2 mA VCC – 0.7 V VOH2 Output high voltage (RST) –IOH = 400 µA 2.4 V –IOH = 120 µA 0.8 VDD V RRST Internal reset pull-down resistor 40 225 k Ω CIO Pin capacitance Test freq = 1 MHz, Tamb = 25°C 10 pF Analog Inputs AVDD Analog supply voltage: 87C5549 AVDD = VDD±0.2 V 2.7 5.5 V AIDD Analog supply current: operating: Port 5 = 0 to AVDD 1.2 mA AIID Idle mode: 87C554 50 µA AIPD Power-down mode: 87C554 2 V < AVPD < AVDD max 50 µA |
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