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80C554 Datasheet(PDF) 6 Page - NXP Semiconductors |
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80C554 Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 76 page  Philips Semiconductors Preliminary specification 80C554/83C554/87C554 80C51 8-bit microcontroller – 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP 2000 Nov 10 6 PIN DESCRIPTION (Continued) PIN NO. MNEMONIC LQFP TYPE NAME AND FUNCTION P4.0-P4.7 14–21 I/O Port 4: 8-bit programmable I/O port. Alternate functions include: 14–19 O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. 20, 21 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. Port 4 has four modes selected on a per bit basis by writing to the P4M1 and P4M2 registers as follows: P4M1.x P4M2.x Mode Description 0 0 Pseudo-bidirectional (standard c51 configuration; default) 0 1 Push-Pull 1 0 High impedance 1 1 Open drain P5.0-P5.6 2–8 I Port 5: 8-bit input port. ADC0-ADC7 (P5.0-P5.7): Alternate function: Seven input channels to the ADC. RST 22 I/O Reset: Input to reset the 87C554. It also provides a reset pulse as output when timer T3 overflows. XTAL1 40 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. XTAL2 39 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used. VSS 41–42 I Digital ground. PSEN 51 O Program Store Enable: Active-low read strobe to external program memory. ALE/PROG 52 O Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG) during EPROM programming. EA/VPP 53 I External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 16,384. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. This pin also receives the 12.75 V programming supply voltage (VPP) during EPROM programming. AVREF– 62 I Analog to Digital Conversion Reference Resistor: Low-end. AVREF+ 63 I Analog to Digital Conversion Reference Resistor: High-end. AVSS 64 I Analog Ground AVDD 1 I Analog Power Supply NOTE: 1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5 V or VSS – 0.5 V, respectively. |
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