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CD4070BMS Datasheet(PDF) 6 Page - Renesas Technology Corp |
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CD4070BMS Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 8 page CD4070BMS, CD4077BMS FN3322 Rev 0.00 Page 6 of 8 December 1992 Schematics FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070BMS (1 OF 4 IDENTICAL GATES) FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077BMS (1 OF 4 IDENTICAL GATES) n p VSS VDD ALL INPUTS PROTECTED BY * CMOS PROTECTION NETWORK VDD VSS n p B * 2 (5, 9, 12) n p VSS VDD A * 1 (6, 8, 13) n p VSS VDD n p p J 3 (4, 10, 11) TRUTH TABLE CD4070BMS 1 OF 4 GATES AB J 000 101 011 110 1 = High Level 0 = Low Level J = A B n p VSS VDD ALL INPUTS PROTECTED BY * CMOS PROTECTION NETWORK VDD VSS n p B * 2 (5, 9, 12) n p VSS VDD A * 1 (6, 8, 13) n VSS n p J 3 (4, 10, 11) TRUTH TABLE CD4077BMS 1 OF 4 GATES AB J 001 100 010 111 1 = High Level 0 = Low Level J = AB n p VDD |
Similar Part No. - CD4070BMS |
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Similar Description - CD4070BMS |
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