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TPA3118D2 Datasheet(PDF) 6 Page - Texas Instruments |
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TPA3118D2 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 45 page 6 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G – APRIL 2012 – REVISED DECEMBER 2017 www.ti.com Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) For the PCB layout please see the TPA3130D2EVM user guide. (3) For the PCB layout please see the TPA3118D2EVM user guide. (4) The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high. 6.4 Thermal Information THERMAL METRIC(1) TPA3130D2 TPA3118D2 TPA3116D2 UNIT DAP(2) DAP(3) DAD(4) 32 PINS 32 PINS 32 PINS RθJA Junction-to-ambient thermal resistance 36 22 14 °C/W ψJT Junction-to-top characterization parameter 0.4 0.3 1.2 ψJB Junction-to-board characterization parameter 5.9 4.7 5.7 6.5 DC Electrical Characteristics TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 15 mV ICC Quiescent supply current SDZ = 2 V, No load or filter, PVCC = 12 V 20 35 mA SDZ = 2 V, No load or filter, PVCC = 24 V 32 50 ICC(SD) Quiescent supply current in shutdown mode SDZ = 0.8 V, No load or filter, PVCC = 12 V <50 µA SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 400 rDS(on) Drain-source on-state resistance, measured pin to pin PVCC = 21 V, Iout = 500 mA, TJ = 25°C 120 mΩ G Gain (BTL) R1 = 5.6 kΩ, R2 = Open 19 20 21 dB R1 = 20 kΩ, R2 = 100 kΩ 25 26 27 R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 dB R1 = 47 kΩ, R2 = 75 kΩ 35 36 37 G Gain (SLV) R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 dB R1 = 75 kΩ, R2 = 47 kΩ 25 26 27 R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 dB R1 = 100 kΩ, R2 = 16 kΩ 35 36 37 ton Turn-on time SDZ = 2 V 10 ms tOFF Turn-off time SDZ = 0.8 V 2 µs GVDD Gate drive supply IGVDD < 200 µA 6.4 6.9 7.4 V VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms 6.75 7.90 8.75 V |
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