December 1990

2

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74HC/HCT573

FEATURES

• Inputs and outputs on opposite

sides of package allowing easy

interface with microprocessors

• Useful as input or output port for

microprocessors/microcomputers

• 3-state non-inverting outputs for

bus oriented applications

• Common 3-state output enable

input

• Functionally identical to the “563”

and “373”

• Output capability: bus driver

GENERAL DESCRIPTION

The 74HC/HCT573 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard no.

7A.

The 74HC/HCT573 are octal D-type

transparent latches featuring

separate D-type inputs for each latch

and 3-state outputs for bus oriented

applications.

A latch enable (LE) input and an

output enable (OE) input are common

to all latches.

The “573” consists of eight D-type

transparent latches with 3-state true

outputs. When LE is HIGH, data at

condition the latches are transparent,

i.e. a latch output will change state

each time its corresponding D-input

changes.

When LE is LOW the latches store the

information that was present at the

D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the

8 latches are available at the outputs.

When OE is HIGH, the outputs go to

the high impedance OFF-state.

Operation of the OE input does not

affect the state of the latches.

The “573” is functionally identical to

the “563” and “373”, but the “563” has

inverted outputs and the “373” has a

different pin arrangement.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

14

17

ns

15

15

ns

input capacitance

3.5

3.5

pF

power dissipation capacitance per latch notes 1 and 2

26

26

pF