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IDT72V3624 Datasheet(PDF) 13 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 13 Page - Integrated Device Technology |
13 / 34 page ![]() 13 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Synchronized Synchronized Number of Words in FIFO Memory(1,2) to CLKA to CLKB IDT72V3624(3) IDT72V3634(3) IDT72V3644(3) EFA/ORA AEA AFB FFB/IRB 000 L L H H 1 to X2 1 to X2 1 to X2 H L H H (X2+1) to [256-(Y2+1)] (X2+1) to [512-(Y2+1)] (X2+1) to [1,024-(Y2+1)] H H H H (256-Y2) to 255 (512-Y2) to 511 (1,024-Y2) to 1,023 H H L H 256 512 1,024 H H L L TABLE 4 .I.O1 .LAG OPERATION (IDT Standard and .W.T modes) TABLE 5 .I.O2 .LAG OPERATION (IDT Standard and .W.T modes) Synchronized Synchronized Number of Words in FIFO Memory(1,2) to CLKB to CLKA IDT72V3624(3) IDT72V3634(3) IDT72V3644(3) EFB/ORB AEB AFA FFA/IRA 00 0 L L H H 1 to X1 1 to X1 1 to X1 H L H H (X1+1) to [256-(Y1+1)] (X1+1) to [512-(Y1+1)] (X1+1) to [1,024-(Y1+1)] H H H H (256-Y1) to 255 (512-Y1) to 511 (1,024-Y1) to 1,023 H H L H 256 512 1,024 H H L L In the IDT Standard mode, the Empty Flag ( EFA,EFB)functionisselected. When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for reading to the output register. When the Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT and IDT Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its outputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors a write pointer and read pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. In FWFT mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FlFO output register and three cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta- neously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. In IDT Standard mode, from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag isLOWifawordinmemoryisthenextdatatobesenttotheFlFOoutputregister andtwocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsed sincethetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then can data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle can be the first synchronization cycle (see Figures 15, 16, 17, and 18). FULL/INPUT READY FLAGS ( FFA/IRA, FFB/IRB) This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB) function is selected. In IDT Standard mode, the Full Flag ( FFA and FFB) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites to the FIFO are ignored. NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming. 4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode. NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming. 4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode. |
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