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IDT72V3624 Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 34 page  11 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 SPM FS1/ SEN FS0/SD MRS1 MRS2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2) HH H ↑ X64 X HH H ↑↑ 64 64 HH L ↑ X16 X HH L ↑↑ 16 16 HL H ↑ X8 X HL H ↑↑ 88 HL L ↑↑ Parallel programming via Port A Parallel programming via Port A LH L ↑↑ Serial programming via SD Serial programming via SD LH H ↑↑ Reserved Reserved LL H ↑↑ Reserved Reserved LL L ↑↑ Reserved Reserved labeled Y2. The index of each register name corresponds to its FIFO number. TheoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofaFIFO, programmed in parallel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1). SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard and FWFT modes. — PRESET VALUES ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith oneofthethreepresetvalueslistedinTable1,theSerialProgramMode( SPM) andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-to-HIGH transition of its Master Reset input ( MRS1, MRS2). For example, to load the preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when FlFO1reset( MRS1)returnsHIGH.Flag-offsetregistersassociatedwithFIFO2 are loaded with one of the preset values in the same way with FIFO2 Master Reset( MRS2),toggledsimultaneouslywithFIFO1MasterReset(MRS1).For relevant preset value loading timing diagram, see Figure 3. — PARALLEL LOAD FROM PORT A To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master Reset on both FlFOs simultaneously with SPMHIGHandFS0andFS1LOW during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the first four writes to FIFO1 do not store data in the RAM but load the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3624, IDT72V3634, or IDT72V3644, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 252 for the IDT72V3624; 1 to 508 for the IDT72V3634; and 1 to 1,020 for the IDT72V3644. After all the offset registers are programmed from Port A, the Port B Full/Input Ready flag ( FFB/IRB)issetHIGH,andbothFIFOsbeginnormaloperation.RefertoFigure 5foratimingdiagramillustrationofparallelprogrammingoftheflagoffsetvalues. — SERIAL LOAD ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset with SPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH transitionof MRS1andMRS2.Afterthisresetiscomplete,theXandYregister values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/ SEN input is LOW. There are 32-, 36-, or 40- bit writes needed to complete the programming for the IDT72V3624, IDT72V3634, or IDT72V3644, respectively. The four registers are written in theorderY1,X1,Y2,andfinally,X2. Thefirst-bitwritestoresthemostsignificant bitoftheY1registerandthelast-bitwritestorestheleastsignificantbitoftheX2 register.Eachregistervaluecanbeprogrammedfrom1to252(IDT72V3624), 1 to 508 (IDT72V3634), or 1 to 1,020 (IDT72V3644). When the option to program the offset registers serially is chosen, the Port AFull/InputReady( FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten. FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready ( FFB/ IRB) flag also remains LOW throughout the serial programming process, until allregisterbitsarewritten. FFB/IRBissetHIGHbytheLOW-to-HIGHtransition ofCLKBafterthelastbitisloadedtoallownormalFIFO2operation.SeeFigure 6 for Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes) timing diagram. FIFO WRITE/READ OPERATION ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect ( CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh- impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are active outputs when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs byaLOW-to-HIGHtransitionofCLKAwhen CSAisLOW,W/RAisLOW,ENA is HIGH, MBA is LOW, and EFA/ORAisHIGH(seeTable2).FIFOreadsand writes on Port A are independent of any concurrent Port B operation. The Port B control signals are identical to those of Port A with the exception thatthePortBWrite/Readselect( W/RB)istheinverseofthePortAWrite/Read select (W/ RA).ThestateofthePortBdata(B0-B35)linesiscontrolledbythe Port B Chip Select ( CSB) and Port B Write/Read select (W/RB).TheB0-B35 lines are in the high-impedance state when either CSB is HIGH or W/RB is NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. TABLE 1 .LAG PROGRAMMING |
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