IDT72V3624 datasheet(8/34 Pages) IDT

Part #	IDT72V3624

Description	3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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COMMERCIALTEMPERATURERANGE

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

TIMING REQUIREMENTS OVER RECOMMENDED RANGES O. SUPPLY

VOLTAGE AND OPERATING .REE-AIR TEMPERATURE

IDT72V3624L10(1)

IDT72V3624L15

IDT72V3634L10(1)

IDT72V3634L15

IDT72V3644L10(1)

IDT72V3644L15

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

fS

Clock Frequency, CLKA or CLKB

—

100

—

66.7

MHz

tCLK

Clock Cycle Time, CLKA or CLKB

10

—

15

—

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

4.5

—

6

—

ns

tCLKL

Pulse Duration, CLKA and CLKB LOW

4.5

—

6

—

ns

tDS

Setup Time, A0-A35 before CLKA

↑ and B0-B35 before CLKB↑

3—

4

—

ns

tENS1

Setup Time

CSA before CLKA

↑; CSBbeforeCLKB↑4

—

4.5

—

ns

tENS2

Setup Time ENA, W/

RA and MBA before CLKA

↑; ENB, W/RB and MBB

3

—

4.5

—

ns

before CLKB

↑

tRSTS

Setup Time,

MRS1, MRS2, PRS1, or PRS2 LOW before CLKA

↑ or CLKB↑(2)

5—

5

—

ns

tFSS

Setup Time, FS0 and FS1 before

MRS1 and MRS2 HIGH

7.5

—

7.5

—

ns

tBES

Setup Time, BE/

FWFT before MRS1 and MRS2 HIGH

7.5

—

7.5

—

ns

tSPMS

Setup Time,

SPM before MRS1 and MRS2 HIGH

7.5

—

7.5

—

ns

tSDS

Setup Time, FS0/SD before CLKA

↑

3—

4

—

ns

tSENS

Setup Time, FS1/

SEN before CLKA

↑

3—

4

—

ns

tFWS

Setup Time, BE/

FWFT before CLKA

↑

0—

0

—

ns

tDH

Hold Time, A0-A35 after CLKA

↑ and B0-B35 after CLKB↑

0.5

—

1

—

ns

tENH

Hold Time,

CSA, W/RA, ENA, and MBA after CLKA

↑; CSB, W/RB, ENB, and

0.5

—

1

—

ns

MBB after CLKB

↑

tRSTH

Hold Time,

MRS1, MRS2, PRS1 or PRS2 LOW after CLKA

↑ or CLKB↑(2)

4—

4

—

ns

tFSH

Hold Time, FS0 and FS1 after

MRS1 and MRS2 HIGH

2

—

2

—

ns

tBEH

Hold Time, BE/

FWFT after MRS1 and MRS2 HIGH

2

—

2

—

ns

tSPMH

Hold Time,

SPM after MRS1 and MRS2 HIGH

2

—

2

—

ns

tSDH

Hold Time, FS0/SD after CLKA

↑

0.5

—

1

—

ns

tSENH

Hold Time, FS1/

SEN HIGH after CLKA

↑

0.5

—

1

—

ns

tSPH

Hold Time, FS1/

SEN HIGH after MRS1 and MRS2 HIGH

2

—

2

—

ns

tSKEW1(3)

Skew Time between CLKA

↑ and CLKB↑ for EFA/ORA, EFB/ORB,FFA/IRA,

5

—

7.5

—

ns

and

FFB/IRB

tSKEW2(3,4)

Skew Time between CLKA

↑ and CLKB↑ for AEA, AEB, AFA, and AFB

12

—

12

—

ns

NOTES:

1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0

° to +70°C; JEDEC JESD8-A compliant.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.

5. Industrial temperature range is available by special order.

Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0

°Cto +70°C; JEDEC JESD8-A compliant

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