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IDT72V3624 Datasheet(PDF) 6 Page - Integrated Device Technology

Part # IDT72V3624
Description  3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V3624 Datasheet(HTML) 6 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING .REE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
Symbol
Rating
Commercial
Unit
VCC
Supply Voltage Range
–0.5 to +4.6
V
VI(2)
Input Voltage Range
–0.5 to VCC+0.5
V
VO(2)
Output Voltage Range
–0.5 to VCC+0.5
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
±20
mA
IOK
Output Clamp Current (VO = < 0 or VO > VCC)
±50
mA
IOUT
Continuous Output Current (VO = 0 to VCC)
±50
mA
ICC
Continuous Current Through VCC or GND
±400
mA
TSTG
Storage Temperature Range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
ABSOLUTE MAXIMUM RATINGS OVER OPERATING .REE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
RECOMMENDED OPERATING CONDITIONS
NOTES:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0
° to +70° C; JEDEC JESD8-A compliant.
2. All typical values are at VCC = 3.3V, TA = 25
°C.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
5. Industrial temperature range is available by special order.
NOTE:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0
° to +70° C; JEDEC JESD8-A compliant.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC(1)
Supply Voltage
3.0
3.3
3.6
V
VIH
High-Level Input Voltage
2
VCC+0.5
V
VIL
Low-Level Input Voltage
0.8
V
IOH
High-Level Output Current
–4
mA
IOL
Low-Level Output Current
8
mA
TA
OperatingTemperature
0
70
°C
IDT72V3624
IDT72V3634
IDT72V3644
Commercial
tCLK = 10(1), 15ns
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max.
Unit
VOH
Output Logic "1" Voltage
VCC = 3.0V,
IOH = –4 mA
2.4
V
VOL
Output Logic "0" Voltage
VCC = 3.0V,
IOL = 8 mA
0.5
V
ILI
Input Leakage Current (Any Input)
VCC = 3.6V,
VI = VCC or 0
±10
µ A
ILO
OutputLeakageCurrent
VCC = 3.6V,
VO = VCC or 0
±10
µ A
ICC2(3)
Standby Current (with CLKA and CLKB running)
VCC = 3.6V,
VI = VCC - 0.2V or 0
5
mA
ICC3(3)
Standby Current (no clocks running)
VCC = 3.6V,
VI = VCC - 0.2V or 0
1
mA
CIN(4)
InputCapacitance
VI = 0,
f = 1 MHz
4
pF
COUT(4)
OutputCapacitance
VO = 0,
f = 1 MHZ
8
pF


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