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IDT72V3624 Datasheet(PDF) 30 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 30 Page - Integrated Device Technology |
30 / 34 page 30 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Figure 25. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes) Figure 23. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes) Figure 24. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes) NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write ( CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively. NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write ( CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 3. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown. 2. FIFO1 Write ( CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644. 4. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively. AEB CLKA ENB 4664 drw25 ENA CLKB 2 1 tENH tSKEW2 tPAE tPAE tENH X1 Words in FIFO1 (X1+1) Words in FIFO1 (1) tENS2 tENS2 AEA CLKB ENA 4664 drw26 ENB CLKA 2 1 tENH tSKEW2 tPAE tPAE tENH (X2+1) Words in FIFO2 X2 Words in FIFO2 (1) tENS2 tENS2 AFA CLKA ENB 4664 drw27 ENA CLKB 12 tSKEW2 tENH tPAF tENH tPAF [D-(Y1+1)] Words in FIFO1 (D-Y1) Words in FIFO1 (1) tENS2 tENS2 |
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