IDT72V3624 datasheet(3/34 Pages) IDT

Part #	IDT72V3624

Description	3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

coincident. The enables for each port are arranged to provide a simple

bidirectional interface between microprocessors and/or buses with synchro-

nous control.

CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox

registers. The mailbox registers’ width matches the selected Port B bus width.

Each Mailbox register has a flag (

MBF1 and MBF2) to signal when new mail

has been stored.

TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial

Reset.MasterResetinitializesthereadandwritepointerstothefirstlocationof

the memory array, configures the FIFO for Big- or Little-Endian byte arrange-

ment and selects serial flag programming, parallel flag programming, or one of

threepossibledefaultflagoffsetsettings,8,16or64.TherearetwoMasterReset

pins,

MRS1 and MRS2.

PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe

memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,

programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset

is useful since it permits flushing of the FIFO memory without changing any

configuration settings. Each FIFO has its own, independent Partial Reset pin,

PRS1 and PRS2.

These devices have two modes of operation: In the IDT Standard mode,

the first word written to an empty FIFO is deposited into the memory array. A

read operation is required to access that word (along with all other words

residinginmemory).IntheFirstWordFallThroughmode (FWFT),thefirstlong-

word (36-bit wide) written to an empty FIFO appears automatically on the

outputs, no read operation is required (Nevertheless, accessing subsequent

words does necessitate a formal read request). The state of the BE/

FWFTpin

during FIFO operation determines the mode in use.

Each FIFO has a combined Empty/Output Ready Flag (

EFA/ORA and

EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB).

The

EFandFFfunctionsareselectedintheIDTStandardmode.EFindicates

whether or not the FIFO memory is empty.

FF shows whether the memory is

full or not. The IR and OR functions are selected in the First Word Fall Through

mode. IR indicates whether or not the FIFO has available memory locations.

OR shows whether the FIFO has data available for reading or not. It marks the

presence of valid data on the outputs.

Each FIFO has a programmable Almost-Empty flag (

AEAandAEB)and

aprogrammableAlmost-Fullflag(

AFAandAFB). AEAandAEB indicatewhen

aselectednumberofwordsremainintheFIFOmemory.

AFAandAFBindicate

when the FIFO contains more than a selected number of words.

FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport

clockthatwritesdataintoitsarray.

EFA/ORA,EFB/ORB,AEAandAEBaretwo-

stage synchronized to the port clock that reads data from its array. Program-

mable offsets for

AEA, AEB, AFAand AFB areloaded inparallelusingPortA

or in serial via the SD input. The Serial Programming Mode pin (

SPM) makes

thisselection.Threedefaultoffsetsettingsarealsoprovided.The

AEAandAEB

threshold can be set at 8, 16 or 64 locations from the empty boundary and the

AFAandAFBthresholdcanbesetat8,16or64locationsfromthefullboundary.

AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset.

Two or more devices may be used in parallel to create wider data paths.

If, at any time, the FIFO is not actively performing a function, the chip will

automatically power down. During the power down state, supply current

consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol

inputs) will immediately take the device out of the power down state.

The IDT72V3624/72V3634/72V3644 are characterized for operation from

0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available. They

are fabricated using IDT’s high speed, submicron CMOS technology.

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