IDT72V3624 datasheet(28/34 Pages) IDT

Part #	IDT72V3624

Description	3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.

2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.

Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)

CSA

ORA

W/

RA

MBA

ENA

A0-A35

CLKA

IRB

CLKB

CSB

4664 drw23

W/RB

B0-B35

MBB

ENB

12

tCLK

tCLKH

tCLKL

tENH

tA

tSKEW1

tCLK

tCLKH

tCLKL

tWFF

tENH

tDS

tDH

To FIFO2

Previous Word in FIFO2 Output Register

Next Word From FIFO2

FIFO2 FULL

LOW

HIGH

LOW

(1)

Write

tENS2

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IDT72V3624 Datasheet(PDF) 28 Page - Integrated Device Technology

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