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IDT72V3624 Datasheet(PDF) 27 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 27 Page - Integrated Device Technology |
27 / 34 page ![]() 27 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Figure 20. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode) Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode) NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown. 2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown. 2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively. CSB ORB W/RB MBB ENB B0-B35 CLKB IRA CLKA CSA 4664 drw21 W/ RA A0-A35 MBA ENA 12 tCLK tCLKH tCLKL tENS2 tENH tA tSKEW1 tCLK tCLKH tCLKL tWFF tENS2 tENS2 tDS tENH tENH tDH To FIFO1 Previous Word in FIFO1 Output Register Next Word From FIFO1 LOW HIGH LOW HIGH LOW HIGH (1) FIFO1 Full tWFF Write CSB EFB MBB ENB B0-B35 CLKB FFA CLKA CSA 4664 drw22 W/ RA 12 A0-A35 MBA ENA tCLK tCLKH tCLKL tENH tA tSKEW1 tCLK tCLKH tCLKL tDS tENH tENH tDH To FIFO1 Previous Word in FIFO1 Output Register Next Word From FIFO1 LOW W/RB HIGH LOW HIGH LOW HIGH (1) FIFO1 Full tWFF tWFF Write tENS2 tENS2 tENS2 |
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