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IDT72V3624 Datasheet(PDF) 26 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 26 Page - Integrated Device Technology |
26 / 34 page ![]() 26 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. 2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. Figure 18. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode) CSB W/RB MBB FFB B0-B35 CLKA EFA CSA W/ RA MBA ENB ENA A0-A35 CLKB 12 4664 drw20 tCLKH tCLKL tCLK tENS2 tENS2 tENH tENH tDS tDH tSKEW1 (1) tCLK tCLKL tENS2 tENH tA W1 FIFO2 Empty LOW LOW LOW LOW LOW tCLKH W1 HIGH tREF tREF |
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