IDT72V3624 datasheet(25/34 Pages) IDT

Part #	IDT72V3624

Description	3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.

If the time between the CLKB edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA

cycle later than shown.

2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)

CSB

W/RB

MBB

IRB

B0-B35

CLKA

ORA

CSA

W/

RA

MBA

ENB

ENA

A0-A35

CLKB

4664 drw19

12

3

tCLKH

tCLKL

tCLK

tENS2

tENH

tDS

tDH

tSKEW1

(1)

tCLK

tCLKH

tREF

tENS2

tENH

tA

Old Data in FIFO2 Output Register

W1

FIFO2 Empty

tCLKL

LOW

HIGH

W1

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