IDT72V3624 datasheet(23/34 Pages) IDT

Part #	IDT72V3624

Description	3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.

If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB

cycle later than shown.

2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.

Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)

CSA

W/

RA

MBA

IRA

A0-A35

CLKB

ORB

CSB

W/RB

MBB

ENA

ENB

B0-B35

CLKA

4664 drw17

12

3

tCLKH

tCLKL

tCLK

tENS2

tENH

tDS

tDH

tSKEW1

tCLKL

tREF

tENS2

tENH

tA

Old Data in FIFO1 Output Register

W1

FIFO1 Empty

LOW

HIGH

LOW

HIGH

LOW

tCLKH

W1

HIGH

(1)

tCLK

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