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IDT72V3624 Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 34 page ![]() 2 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 PIN CON.IGURATION TQFP (PK128-1, order code: PF) TOP VIEW W/ RA CLKB 4664 drw02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ENA CLKA GND A35 A34 A33 A32 Vcc A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/ FWFT GND A22 Vcc A21 A20 A19 A18 GND A17 A16 A15 A14 A13 Vcc A12 GND A11 A10 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 PRS2 Vcc B35 B34 B33 B32 GND GND B31 B30 B29 B28 B27 B26 Vcc B25 B24 BM GND B23 B22 B21 B20 B19 B18 GND B17 B16 Vcc B15 B14 B13 B12 GND B11 B10 INDEX SIZE DESCRIPTION: TheIDT72V3624/72V3634/72V3644arepinandfunctionallycompatible versions of the IDT723624/723634/723644, designed to run off a 3.3V supply forexceptionallylow-powerconsumption. Thesedevicesare monolithic,high- speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory whichsupportsclockfrequenciesupto100MHzandhasreadaccesstimesas fast as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can beinputandoutputin36-bit,18-bit,or9-bitformatswithachoiceofBig-orLittle- Endianconfigurations. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or |
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