18

COMMERCIALTEMPERATURERANGE

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)

Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)

NOTES:

FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising

FFB/IRB may transition HIGH one CLKB cycle later than shown.

2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until

FFA/IRA and FFB/IRB is set HIGH.

3. Programmable offsets are written serially to the SD input in the order

AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).

NOTES:

FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising

FFB/IRB may transition HIGH one CLKB cycle later than shown.

2.

CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

4664 drw07

CLKA

MRS1,

MRS2

FFA/IRA

CLKB

FFB/IRB

A0-A35

FS1,FS0

ENA

4

0,0

AFA Offset

(Y1)

AEB Offset

(X1)

AFB Offset

(Y 2)

AEA Offset

(X 2)

First Word to FIFO1

12

(1)

SPM

1

2

CLKA

FFA/IRA

FS0/SD(3)

FS1/

SEN

AEA Offset (X2) LSB

AFA Offset (Y1) MSB

MRS1,

MRS2

4

4664 drw08

CLKB

4

SPM

FFB/IRB