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IDT72V3624 Datasheet(PDF) 17 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 17 Page - Integrated Device Technology |
17 / 34 page ![]() 17 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 NOTES: 1. Partial Reset is performed in the same manner for FIFO2. 2. MRS1 must be HIGH during Partial Reset. 3. If BE/ FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW. Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes) Figure 4. FIFO1 Partial Reset(1) (IDT Standard and FWFT Modes) NOTES: 1. FIFO2 Master Reset ( MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2. 2. PRS1 must be HIGH during Master Reset. 3. If BE/ FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW. CLKA MRS1 FFA/IRA AEB AFA MBF1 CLKB EFB/ORB FS1,FS0 4664 drw05 tRSTS tRSTH tFSH tFSS tWFF tWFF tREF tRSF 0,1 tRSF tRSF BE BE/ FWFT SPM FWFT tBES tSPMS tBEH tSPMH tFWS (3) CLKA PRS1 FFA/IRA AEB AFA MBF1 CLKB EFB/ORB 4664 drw06 tRSTS tRSTH tREF(3) tRSF tRSF tRSF tWFF tWFF |
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