December 1990

2

Philips Semiconductors

Product specification

Octal D-type flip-flop with data enable;

positive-edge trigger

74HC/HCT377

FEATURES

• Ideal for addressable register applications

• Data enable for address and data synchronization

applications

• Eight positive-edge triggered D-type flip-flops

• See “273” for master reset version

• See “373” for transparent latch version

• See “374” for 3-state version

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT377 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT377 have eight edge-triggered, D-type

flip-flops with individual D inputs and Q outputs. A common

clock (CP) input loads all flip-flops simultaneously when

the data enable (E) is LOW. The state of each D input, one

set-up time before the LOW-to-HIGH clock transition, is

The E input must be stable only one set-up time prior to the

LOW-to-HIGH transition for predictable operation.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

13

14

ns

maximum clock frequency

77

53

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per flip-flop

notes 1 and 2

20

20

pF