1998 Jul 08

2

Philips Semiconductors

Product specification

Hex D-type flip-flop with reset; positive-edge trigger

74HC/HCT174

FEATURES

• Six edge-triggered D-type flip-flops

• Asynchronous master reset

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT174 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT174 have six edge-triggered D-type

flip-flops with individual D inputs and Q outputs. The

common clock (CP) and master reset (MR) inputs load and

reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D

input, one set-up time prior to the LOW-to-HIGH clock

transition, is transferred to the corresponding output of the

flip-flop.

A LOW level on the MR input forces all outputs LOW,

independently of clock or data inputs.

The device is useful for applications requiring true outputs

only and clock and master reset inputs that are common to

all storage elements.

QUICK REFERENCE DATA

Notes

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

17

18

ns

13

17

ns

maximum clock frequency

99

69

MHz

input capacitance

3.5

3.5

pF

power dissipation

capacitance per flip-flop

notes 1 and 2

17

17

pF