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73K221AL Datasheet(PDF) 9 Page - TDK Electronics |
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73K221AL Datasheet(HTML) 9 Page - TDK Electronics |
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9 / 26 page  73K222BL V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid 9 CONTROL REGISTER 0 D7 D6 D5 D4 D3 D2 D1 D0 CR0 000 MODUL. OPTION 0 TRANSMIT MODE 3 TRANSMIT MODE 2 TRANSMIT MODE 1 TRANSMIT MODE 0 TRANSMIT ENABLE ANSWER/ ORIGINATE BIT NO. NAME CONDITION DESCRIPTION 0 Selects answer mode (transmit in high band, receive in low band). D0 Answer/ Originate 1 Selects originate mode (transmit in low band, receive in high band). 0 Disables transmit output at TXA. D1 Transmit Enable 1 Enables transmit output at TXA. Note: TX Enable must be set to 1 to allow Answer Tone and DTMF Transmission as well as data carriers. D5 D4 D3 D2 00 0 0 Selects power-down mode. All functions disabled except digital interface. 0 0 0 1 Internal synchronous mode. In this mode TXCLK is an internally derived 1200 Hz signal. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. Receive data is clocked out of RXD on the falling edge of RXCLK. 0 0 1 0 External synchronous mode. Operation is identical to internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz ± 0.01% clock must be supplied externally. 0 0 1 1 Slave synchronous mode. Same operation as other synchronous modes. TXCLK is connected internally to the RXCLK pin in this mode. 0 1 0 0 Selects PSK asynchronous mode - 8 bits/character (1 start bit, 6 data bits, 1 stop bit). 0 1 0 1 Selects PSK asynchronous mode - 9 bits/character (1 start bit, 7 data bits, 1 stop bit). 0 1 1 0 Selects PSK asynchronous mode - 10 bits/character (1 start bit, 8 data bits, 1 stop bit). 0 1 1 1 Selects PSK asynchronous mode - 11 bits/character (1 start bit, 8 data bits, Parity and 1 or 2 stop bits). D5, D4, D3, D2 Transmit Mode 1 1 0 0 Selects FSK operation. D6 0 Not used; must be written as a “0.” |
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