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V3020SO8B Datasheet(PDF) 11 Page - EM Microelectronic - MARIN SA |
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V3020SO8B Datasheet(HTML) 11 Page - EM Microelectronic - MARIN SA |
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11 / 17 page  R V3020 Copyright © 2005, EM Microelectronic-Marin SA 11 www.emmicroelectronic.com Pin Description Pin SO8 TSSO8 Name Function 1 3 XI 32 kHz crystal input 2 4 XO 32 kHz crystal output 3 5 CS Chip select input 4 6 VSS Ground supply 5 7 I/O Data input and output 6 8 RD Intel RD , Motorola DS (or tie to CS ) 7 1 WR Intel WR , Motorola R/ W 8 2 VDD Positive supply Table 5 Functional Description Serial Communication The V3020 resides on the parallel data and address buses as a standard peripheral (see Fig.15 and 16). Address decoding provides an active low chip select ( CS ) to the device. For Intel compatible bus timing the control signals RD and WR pulse and CS are used for a single bit read or write (see Fig. 7a and 7b). Two options exist for Motorola compatible bus timing. The first is to use the control signals DS with R/ W and CS , the second is to tie the RD input to CS and use the control signals R/ W and CS (see Fig. 7a and 7c). Data transfer is accomplished through a single input/output line (I/O). Any data bus line can be chosen. A conventional 3 wire serial interface can also be used to communicate with the V3020 (see Fig. 17). Communication Cycles The V3020 has 3 serial communication cycles. These are: 1) Read data cycle 2) Write data cycle 3) Address command cycle A communication cycle always begins by writing the 4 address bits, A0 to A3. A microprocessor read from the V3020 cannot begin a communication cycle. Read and write data cycles are similar and consist of 4 address bits and 8 data bits. The 4 address bits, A0 to A3, define the RAM location and the 8 data bits D0 and D7 provide the relevant information. An address command cycle consists of only 4 address bits. Read Data Cycle A read data cycle commences by writing the 4 RAM address bits (A3, A2, A1 and A0) to the V3020. The LSB, A0, is transmitted first (see Fig. 8a and 8b). Eight microprocessor reads from the V3020 will read the RAM data at this address, beginning with the LSB, D0. The read data cycle finishes on reading the 8 th data bit, D7. Write Data Cycle A write data cycle commences by writing the 4 RAM address bits (A3, A2, A1 and A0) to the V3020. The LSB, A0, is transmitted first (see Fig. 8c and 8d). Eight microprocessor writes to the V3020 will write the new RAM data. The LSB, D0, is loaded first. The write data cycle finishes on writing the 8 th data bit, D7. Address Command Cycle An address command cycle consists of just 4 address bits. The LSB, A0, is transmitted first (see Fig. 8e and 8f). On writing the fourth address bit, A3, the address will be decoded. If the address bits are recognized as one of the command codes E hex or F hex (see Table 6), then the communication cycle is terminated and the corresponding command is executed. Subsequent microprocessor writes to the V3020 begin another communication cycle with the first bit being interpreted as the address LSB, A0. Clock Configuration The V3020 has a reserved clock area and a user RAM area (see Fig. 9). The clock is not directly accessible, it is used for internal time keeping and contains the current time and data. The contents of the RAM is shown in Table 6, it contains a data space and an address command space. The data space is directly accessible. Addresses 0 and 1 contain status information (see Tables 7a and 7b), addresses 2 to 5, time data, and addresses 6 to 9, date data. The address command space is used to issue commands to the V3020. RAM Map Address Dec Hex Parameter BCD range Data Space 0 0 Status 0 1 1 Status 1 2 2 Seconds 00-59 3 3 Minutes 00-59 4 4 Hours 00-23 5 5 Day of month 01-31 6 6 Month 01-12 7 7 Year 00-99 8 8 Week day 01-07 9 9 Week number 00-52 Address Command Space 14 E Copy_RAM_to_clock 15 F Copy_clock_to_RAM Table 6 Commands Two commands are available (see Table 6). The Copy_RAM_to_clock command is used to set the current time and date in the clock and the Copy_clock_to_RAM command to copy the current time and date from the clock to the RAM. The Copy_RAM_to_clock command, address data E hex, causes the clock time and date to be overwritten by the time and date stored in the RAM at addresses 2 to 9. Address 1 is also cleared (see section "Time and Date Status Bits"). Prior to using this command, the desired time and date must be loaded into the RAM using write data cycles and the time set lock bit, address 0, bit 4, must be clear (see section "Time Set Lock"). |
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