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W3EG7264S-JD3 Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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W3EG7264S-JD3 Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 11 page ![]() White Electronic Designs 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com May 2005 Rev. 5 W3EG7264S-JD3-D3 PRELIMINARY* Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400 • JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V JEDEC standard 184 pin DIMM package • PCB Height: 30.48mm (1.20") Max NOTE: Consult Factory for availability of: * Lead-Free Products * Vendor source control options * Industrial Temperature option 512MB – 64Mx72 DDR SDRAM UNBUFFERED FEATURES DESCRIPTION The W3EG7264S is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of nine 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. OPERATING FREQUENCIES DDR400 @CL=3 DDR333 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 200MHz 166MHz 133MHz 133MHz 100MHz CL-tRCD-tRP 3-3-3 2.5-3-3 2-2-2 2.5-3-3 2-2-2 |
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